TI中文支持网首先设置了主频 120M，外部晶振20M：
InitSysPll(XTAL_OSC,IMULT_12,FMULT_0,PLLCLK_BY_2);
接着在EPWM初始化的c程序中也完成了设置，增减计数，未进行分频：
EPwm8Regs.TBPRD = Half_Period;
EPwm8Regs.CMPA.bit.CMPA = 0;
EPwm8Regs.CMPB.bit.CMPB = 0;
EPwm8Regs.TBCTR = 0;
EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm8Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm8Regs.TBPHS.bit.TBPHS = 0;
EPwm8Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Pass through
EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm8Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm8Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm8Regs.AQCTLB.bit.CAU = AQ_SET;
同时也在头文件中定义了PWM频率为100K：
#define SYSCLK (120000000UL) // < System Clock frequency
#define PWMFreq (100000) // PWM Frequency
#define Half_Period (SYSCLK/PWMFreq/2) //half period of PWM
但是为什么从引脚上测出来的PWM波是50K的呢？下面一句是CMPA的赋值，写在CLA中。请问是否还有哪里设置了分频而我却不知道的？
EPwm8Regs.CMPA.bit.CMPA = 0.3 * Half_Period;
Green Deng：你好,你用的递增递减模式的话，周期的计算就是
TPWM = 2 x TBPRD x TTBCLK
FPWM = 1 / (TPWM)
输出频率减半的话只能在这两个参数中查找分频问题了。
