TI中文支持网各位工程师好！我现在对AQ模块中的连续软件强制动作有一些问题。如果设置连续软件强制输出低电平，那是不是就意味着从下一个TBCLK边沿开始，EPWM1A与EPWM1B都会持续输出低电平？如果这样的话那前面设置的那些由TB、CC、AQ模块决定PWM的动作不就没有意义了吗？按照下面代码的设置可以输出一个什么样的波形？请各位大佬帮忙解答一下。
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value
EPwm1Regs.CMPB = EPWM1_MAX_CMPB; // Set Compare B value
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // 1分频
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count
EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // the active register load immediately
EPwm1Regs.AQCSFRC.bit.CSFA = FORCE_LOW;
EPwm1Regs.AQCSFRC.bit.CSFB = FORCE_LOW;
Annie Liu：
为更加有效地解决您的问题，我们建议您将问题发布在E2E英文技术论坛上https://e2e.ti.com/support/microcontrollers/c2000/f/171，将由资深的工程师为您提供帮助。我们的E2E英文社区有TI专家进行回复，并得到全球各地工程师的支持，分享他们的知识和经验。
各位工程师好！我现在对AQ模块中的连续软件强制动作有一些问题。如果设置连续软件强制输出低电平，那是不是就意味着从下一个TBCLK边沿开始，EPWM1A与EPWM1B都会持续输出低电平？如果这样的话那前面设置的那些由TB、CC、AQ模块决定PWM的动作不就没有意义了吗？按照下面代码的设置可以输出一个什么样的波形？请各位大佬帮忙解答一下。
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value
EPwm1Regs.CMPB = EPWM1_MAX_CMPB; // Set Compare B value
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // 1分频
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count
EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // the active register load immediately
EPwm1Regs.AQCSFRC.bit.CSFA = FORCE_LOW;
EPwm1Regs.AQCSFRC.bit.CSFB = FORCE_LOW;
Rayna Wang：EPwm1Regs.AQCSFRC.bit.CSFB = FORCE_LOW; 会使EPWM输出强制变低，
有些项目中会在中断判断代码中使用强制置高或置低，实现EPWM输出高低变化，另外其EPWM的interrupt和SOC功能通过配置还可以使用。
