TI中文支持网按用户指南把28335的I2C配置成从机后，用上位机给它发信息，28335进不了I2C的中断，请问是否有相关例程可以参考？
以下附上我自己的I2C初始化程序和ISR，我只是想做一下最简单的测试，让I2C一旦工作就进中断停下
附：
//初始化程序
void init_I2C(void)
{
// Step1: Config Own Address (work as a slave device)
I2caRegs.I2COAR = PCM_I2C_DEVICE_ADDRESS;
// TMS320F28335 I2C Module's own address
// Step2: Config Module Clock
// Tips: clk_module = SYSCLKOUT/(IPSC+1)
#if (CPU_FRQ_150MHZ) // Default – For 150MHz SYSCLKOUT
I2caRegs.I2CPSC.all = 14; // Prescaler – need 7-12 Mhz on module clk (150/15 = 10MHz)
#endif
#if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT
I2caRegs.I2CPSC.all = 9; // Prescaler – need 7-12 Mhz on module clk (100/10 = 10MHz)
#endif
// Step3: Config I2C Bus SCLK clock
// Reference: User Guide Page34 Section5.7.1
I2caRegs.I2CCLKL = 10; // Low-time duration , MUST BE NON ZERO
I2caRegs.I2CCLKH = 5; // High-time duration , MUST BE NON ZERO
// Step4: Config I2C Interrupt Source
// Reference: User Guide Page26; Enable = 1, Disable = 0
I2caRegs.I2CIER.bit.AAS = 1; // Addressed as slave, poll I2CSTR.AAS
I2caRegs.I2CIER.bit.ARBL = 0; // Arbitration lost, poll I2CSTR.ARBL
I2caRegs.I2CIER.bit.ARDY = 0; // Register access ready, poll I2CSTR.ARDY
I2caRegs.I2CIER.bit.NACK = 0; // No-acknowledgement, poll I2CSTR.NACK
I2caRegs.I2CIER.bit.RRDY = 0; // [USED IN NON-FIFO MODE ONLY]Receive data ready, poll I2CSTR.RRDY
I2caRegs.I2CIER.bit.SCD = 0; // Stop condition detected, poll I2CSTR.SCD
I2caRegs.I2CIER.bit.XRDY = 0; // [USED IN NON-FIFO MODE ONLY]Transmit data ready, poll I2CSTR.XRDY
// Step4: Config I2C Mode
/*
// [!!CRITICAL!!] Config it carefully, or I2C won't work
// Reference: User Guide Page23 [NOTICE:USE .all FORMAT]
I2caRegs.I2CMDR.bit.NACKMOD = 0;// [/15] NACK bit, 0:proper ACK bit will be sent, 1:NACK bit will be sent, and NACKMOD will be cleared
I2caRegs.I2CMDR.bit.FREE = 0; // [/14] Free running, 0:breakpoints will work after I2C operation, 1:free run, ignore breakpoints
I2caRegs.I2CMDR.bit.STT = 0; // [/13] Used in MASTER mode only, set to generate a START condition(S) [IRS=1 required]
I2caRegs.I2CMDR.bit.rsvd1 = 0; // [/12] Reserved
I2caRegs.I2CMDR.bit.STP = 0; // [/11] Used in MASTER mode only, set to trig a STOP condition(P) when data count to 0 [IRS=1 required]
// MST & TRX have 4 combinations, corresponding to 4 modes supported by 28335
I2caRegs.I2CMDR.bit.MST = 0; // [/10] MASTER/SLAVE bit, 0:slave, 1:master(change to 0 after a STOP)
I2caRegs.I2CMDR.bit.TRX = 0; // [/09] TRANSMITTER/RECIEVER bit, 0:receiver, 1:transmitter
I2caRegs.I2CMDR.bit.XA = 0; // [/08] Expanded Address, 0:7-bit add, 1: 10-bit add
I2caRegs.I2CMDR.bit.RM = 0; // [/07] Repeated Mode, 0:Non-repeat(set the I2CCNT), 1: Repeat mode(Manually STP required)
I2caRegs.I2CMDR.bit.DLB = 0; // [/06] Digital Loop Back, 0:disable, 1:enable(useful in standalone test)
I2caRegs.I2CMDR.bit.IRS = 0; // [/05] Reset bit, 0: module in reset/disabled, 1: module enabled
I2caRegs.I2CMDR.bit.STB = 0; // [/04] START Byte bit, for low speed
I2caRegs.I2CMDR.bit.FDF = 0; // [/03] Free Data format, 1:enable, XA is ignored, no address, data only
I2caRegs.I2CMDR.bit.BC = 0; // [/02-00] Bit count, 0:default 8bit per byte, 1-7: 1-7 bit per byte
I2caRegs.I2CMDR.bit.IRS = 1; // Take I2C out of reset
*/
I2caRegs.I2CMDR.all = 0x0020; // [RECOMMENDED IN NON-INIT OPERATION] 0000 0000 0010 0000
//Step5: Config FIFO Regs
// Reference: User Guide Page36 [NOTICE:USE .all FORMAT]
/*
I2caRegs.I2CFFTX.bit.rsvd1 = 0; // [/15] Reserved
I2caRegs.I2CFFTX.bit.I2CFFEN = 1; // [/14] Xmit FIFO mode enable, 1:en, 0:dis
I2caRegs.I2CFFTX.bit.TXFFRST = 0; // [/13] Xmit FIFO reset, 0:hold in reset, 1:enable operation
I2caRegs.I2CFFTX.bit.TXFFST; // [/12-08] READONLY, status counts of Xmit FIFO
I2caRegs.I2CFFTX.bit.TXFFINT; // [/07] READONLY, Int Flag of Xmit FIFO
I2caRegs.I2CFFTX.bit.TXFFINTCLR = 0;// [/06] Int Flag Clear, 1:clear TXFFINT
I2caRegs.I2CFFTX.bit.TXFFIENA = 0; // [/05] Xmit FIFO int enable, 1:enable
I2caRegs.I2CFFTX.bit.TXFFIL = 0; // [/04-00] Status level to trig Xmit FIFO int
I2caRegs.I2CFFTX.bit.TXFFRST = 0; // enable Xmit FIFO Operation
I2caRegs.I2CFFTX.bit.TXFFINTCLR = 0;// clear Xmit int at once to avoid detrimental events
*/
I2caRegs.I2CFFTX.all = 0x6000; // [RECOMMENDED IN NON-INIT OPERATION]
/*
I2caRegs.I2CFFRX.bit.rsvd1 = 0; // [/15-14] Reserved
I2caRegs.I2CFFRX.bit.RXFFRST = 0; // [/13] Recv FIFO reset, 0:hold in reset, 1:enable operation
I2caRegs.I2CFFRX.bit.RXFFST; // [/12-08] READONLY, status counts of Recv FIFO
I2caRegs.I2CFFRX.bit.RXFFINT; // [/07] READONLY, Int Flag of Recv FIFO
I2caRegs.I2CFFRX.bit.RXFFINTCLR = 0;// [/06] Int Flag Clear, 1:clear RXFFINT
I2caRegs.I2CFFRX.bit.RXFFIENA = 0; // [/05] Recv FIFO int enable, 1:enable
I2caRegs.I2CFFRX.bit.RXFFIL = 0; // [/04-00] Status level to trig Recv FIFO int
I2caRegs.I2CFFRX.bit.RXFFRST = 0; // enable Xmit FIFO Operation
I2caRegs.I2CFFRX.bit.RXFFINTCLR = 0;// clear Xmit int at once to avoid detrimental events
*/
//I2caRegs.I2CFFRX.all = 0x2040; // [RECOMMENDED IN NON-INIT OPERATION]
I2caRegs.I2CCNT = 1;
return;
}
//I2C的ISR如下
__interrupt void i2c_isr(void)
{
Uint16 IntSource, i;
// Read interrupt source
IntSource = I2caRegs.I2CISRC.all;
// Interrupt source = stop condition detected
if(IntSource == I2C_AAS_ISRC)
{
i=I2caRegs.I2CDRR;
__asm(" ESTOP0");
}
else
{
__asm(" ESTOP0");
for(;;);
}
PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
return;
}
