TI中文支持网硬件：CPU:AM3354 DDR3:H5TQ4G63AFR-PBC
使用的是第三方评估板
阅读评估板代码
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#define DDR3_RATIO 0x80
#define CMD_FORCE 0x00 /* common #def */
#define CMD_DELAY 0x00
#define EMIF_READ_LATENCY 0x0006
#define EMIF_TIM1 0x0CCF36AB
#define EMIF_TIM2 0x265A7FDA
#define EMIF_TIM3 0x501F855F
#define EMIF_SDREF 0x0000093B
#define EMIF_SDCFG 0x61804B32
#define DDR3_DLL_LOCK_DIFF 0x1
#define DDR3_RD_DQS 0x42
#define DDR3_PHY_FIFO_WE 0x39
#define DDR3_INVERT_CLKOUT 0x0
#define DDR3_WR_DQS 0x01
#define DDR3_PHY_WR_DATA 0x3C
#define DDR3_PHY_WRLVL 0x20
#define DDR3_PHY_GATELVL 0x20
#define PHY_RANK0_DELAY 0x01
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_IOCTRL_VALUE 0x18B
得知cl=5,cwl=5,对应DDR的datasheet,
所以ddr的传输频率为667M
我想让DDR的传输频率为800M，做如下修改
将#define EMIF_SDCFG 0x61804B32 改为#define EMIF_SDCFG 0x61805332
结果发现uboot启动不起来了，串口打印如下：
U-Boot SPL 2011.09 (Dec 19 2013 – 16:53:52)
Texas Instruments Revision detection unimplemented
Booting from MMC…
请问如何修改代码，才能让DDR跑到800M？
下面再贴一下pll的配置参数
/* Put the pll config values over here */
#define OSC 24
/* MAIN PLL Fdll = 1 GHZ, */
#define MPUPLL_M_500 500 /* 125 * n */
#define MPUPLL_M_550 550 /* 125 * n */
#define MPUPLL_M_600 600 /* 125 * n */
#define MPUPLL_M_720 720 /* 125 * n */
#define MPUPLL_N 23 /* (n -1 ) *///adu modify 24 -> 23
#define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000 /* 125 * n */
#define COREPLL_N 23 /* (n -1 ) *///adu modify 24 -> 23
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
/*
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
* frequency needs to be set to 960 MHZ. Hence,
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M 960
#define PERPLL_N 23 //adu modify 24 -> 23
#define PERPLL_M2 5
/* DDR Freq is 166 MHZ for now*/
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
#if (CONFIG_AM335X_EVM_IS_13x13 == 1)
#define DDRPLL_M 166 /* M/N + 1 = 25/3 */
#else
#define DDRPLL_M /*266*/303
#endif
#define DDRPLL_N 23 //adu modify 24 -> 23
#define DDRPLL_M2 1
static void ddr_pll_config(void)
{
u32 clkmode, clksel, div_m2;
clkmode = __raw_readl(CM_CLKMODE_DPLL_DDR);
clksel = __raw_readl(CM_CLKSEL_DPLL_DDR);
div_m2 = __raw_readl(CM_DIV_M2_DPLL_DDR);
/* Set the PLL to bypass Mode */
clkmode = (clkmode & 0xfffffff8) | 0x00000004;
__raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
clksel = clksel & (~0x7ffff);
clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N);
__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
div_m2 = div_m2 & 0xFFFFFFE0;
div_m2 = div_m2 | DDRPLL_M2;
__raw_writel(div_m2, CM_DIV_M2_DPLL_DDR);
clkmode = (clkmode & 0xfffffff8) | 0x7;
__raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
}
/*
* Configure the PLL/PRCM for necessary peripherals
*/
void pll_init()
{
// mpu_pll_config(MPUPLL_M_500);
mpu_pll_config(MPUPLL_M_720);
core_pll_config();
per_pll_config();
ddr_pll_config();
/* Enable the required interconnect clocks */
interface_clocks_enable();
/* Enable power domain transition */
power_domain_transition_enable();
/* Enable the required peripherals */
per_clocks_enable();
}
xie david：
回复 Yaoming Qin:
你说的这两个文档我都有看过
将#define EMIF_SDCFG 0x61804B32
//reg_cl = 2 (CAS latency = 5)Value of 2, 4, 6, 8, 10, 12, and 14 (CAS latency of 5, 6, 7, 8, 9, 10, nd 11) are supported for DDR3.
改为#define EMIF_SDCFG 0x61805332
//reg_cl = 4 (CAS latency = 6)
