TI中文支持网我看文件TI_Android_JB_4.2.2_DevKit_4.1.1/kernel/arch/arm/mach-omap2/clock33xx_data.c中MMC2的CLK设置如下
static struct clk mmc_clk = {
.name = "mmc_clk",
.parent = &per_192mhz_clk,
.ops = &clkops_null,
.fixed_div = 2,
.recalc = &omap_fixed_divisor_recalc,
};
static struct clk mmc2_ick = {
.name = "mmc2_ick",
.parent = &l4ls_gclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk mmc2_fck = {
.name = "mmc2_fck",
.clkdm_name = "l3s_clkdm",
.parent = &mmc_clk,
.enable_reg = AM33XX_CM_PER_MMC2_CLKCTRL,
.enable_bit = AM33XX_MODULEMODE_SWCTRL,
.ops = &clkops_omap2_dflt,
.recalc = &followparent_recalc,
};
也就是192/2=96MHz
我现在接一个WIFI设备无法工作，想尝试降低MMC2的频率到48MHz 或 24MHz，不知道是否可以在不影响MMC0和MMC2 的情况下实现？该怎么实现？
多谢指导
Qinghua Zhu：
问题补充：
我示波器测出来mmc2_clk的波形为48MHz的正弦波
是否可以把频率降低为24MHz？是否可以改为方波？
Yaoming Qin：
回复 Qinghua Zhu:
请您查看
18.2.2 MMCHS Clock and Reset ManagementThe MMCHS controller has separate bus interface and functional clocks. The debounce clock is createdby dividing the 96-MHz (48 MHz @ OPP50) clock in the PRCM by two and then dividing the resulting 48-MHz (24 MHz @ OPP50) clock by a fixed 732.4219 (366.2109 @ OPP50) in the Control Module to get a32-kHz clock. This clock is fed back into the PRCM for clock gating. (See the CLK32KDIVRATIO_CTRLregister in Chapter 9, Control Module, for more details).
所以，需要把CPU降频，可以参考 http://processors.wiki.ti.com/index.php/AM335x_Power_Management_User_Guide#Static_CORE_OPP_50
如果排除掉PCB layout的问题，我不觉得这个是需要降频解决的问题
