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AM335x SDK-06.00 GPMC Prefetch NAND EDMA

Hello there,

I have modified some codes to support NAND EDMA,

But something is missed i guess.

Here is the differences:

diff –git a/arch/arm/mach-omap2/board-am335xevm.c b/arch/arm/mach-omap2/board-am335xevm.c
index 9d8a071..fa6be50 100644
— a/arch/arm/mach-omap2/board-am335xevm.c
+++ b/arch/arm/mach-omap2/board-am335xevm.c
@@ -1325,6 +1325,7 @@ static void evm_nand_init(int evm_id, int profile)
         &am335x_nand_timings);
     if (!pdata)
         return;
+    pdata->xfer_type = NAND_OMAP_PREFETCH_DMA;
     pdata->ecc_opt =OMAP_ECC_BCH8_CODE_HW;
     pdata->elm_used = true;
     gpmc_device[0].pdata = pdata;
diff –git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index deb1c1a..2e33788 100644
— a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -26,6 +26,9 @@
 #include <plat/nand.h>
 #include <plat/elm.h>
 
+/* some edma specific hacks which might change */
+#include <mach/edma.h>
+
 #define    DRIVER_NAME    "omap2-nand"
 #define    OMAP_NAND_TIMEOUT_MS    5000
 
@@ -366,12 +369,6 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
     int ret;
     unsigned long tim, limit;
 
–    /* The fifo depth is 64 bytes max.
–     * But configure the FIFO-threahold to 32 to get a sync at each frame
–     * and frame length is 32 bytes.
–     */
–    int buf_len = len >> 6;

     if (addr >= high_memory) {
         struct page *p1;
 
@@ -392,28 +389,36 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
     }
 
     if (is_write) {
–        omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
+        omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
                         info->phys_base, 0, 0);
         omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
–                            dma_addr, 0, 0);
+                            dma_addr, 4, len);
         omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
–                    0x10, buf_len, OMAP_DMA_SYNC_FRAME,
+                    len/4, 1, OMAP_DMA_SYNC_FRAME,
                     OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
     } else {
–        omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
+        omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
                         info->phys_base, 0, 0);
         omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
–                            dma_addr, 0, 0);
+                            dma_addr, 4, len);
         omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
–                    0x10, buf_len, OMAP_DMA_SYNC_FRAME,
+                    len/4, 1, OMAP_DMA_SYNC_FRAME,
                     OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
     }
+#if 0
     /*  configure and start prefetch transfer */
     ret = gpmc_prefetch_enable(info->gpmc_cs,
             PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
     if (ret)
         /* PFPW engine is busy, use cpu copy method */
         goto out_copy;
+#endif
+
+    /* enable interrupts */
+    struct edmacc_param p_ram;
+    edma_read_slot(info->dma_ch, &p_ram);
+    p_ram.opt |= TCINTEN | EDMA_TCC(EDMA_CHAN_SLOT(info->dma_ch));
+    edma_write_slot(info->dma_ch, &p_ram);
 
     init_completion(&info->comp);

So I'm not using GPMC Prefetch, Why can't?

Please HELP me  ; )

If I enable GPMC Prefetch, Kernel won't start up, what's the point here?

[    0.899505] omap-gpmc omap-gpmc: GPMC revision 6.0

[    0.904510] Registering NAND on CS0

[    0.909210] _regulator_get: l3_main.0 supply vdd_core not found, using dummy regulator

[    0.917541] am335x_opp_update: physical regulator not present for core(-22)

[    0.925018] registered am33xx_sr device

[    0.930389] mtdoops: mtd device (mtddev=name/number) must be supplied

[    0.937530] omap2-nand driver initializing

[    0.941925] omap_set_dma_dest_burst_mode: un-supported SDMA wrapper

[    0.948455] omap_set_dma_src_burst_mode: un-supported SDMA wrapper

[    0.955169] NAND device: Manufacturer ID: 0xc2, Chip ID: 0xf1 (Macronix NAND 128MiB 3,3V 8-bit)

[    0.964385] Creating 1 MTD partitions on "omap2-nand.0":

[    0.969940] 0x000000000000-0x000008000000 : "File System"

[    1.026977] OneNAND driver initializing

[    1.031463] UBI: attaching mtd0 to ubi0

[    1.035491] UBI: physical eraseblock size:   131072 bytes (128 KiB)

[    1.041992] UBI: logical eraseblock size:    126976 bytes

[    1.047637] UBI: smallest flash I/O unit:    2048

[    1.052520] UBI: VID header offset:          2048 (aligned 2048)

[    1.058746] UBI: data offset:                4096

<Here is the END of this, Nothing else>

And I know is stops at here:

while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))

       cpu_relax();

It seems that EDMA read data itself, could not using GPMC Prefetch?

Jian Zhou:

这里可以写中文的,请先参考附件的patch。

Tobi Tobi:

回复 Jian Zhou:

http://www.deyisupport.com/question_answer/dsp_arm/sitara_arm/f/25/t/140528.aspx

麻烦帮我看看这个问题, (我没有中文输入法), 我问的是kernel的问题, 你给我的既不是Kernel 也不是 DMA 的 Patch ……………

应该是我没写清楚

user1988910:

回复 Tobi Tobi:

您好,请问你解决这个问题了吗。

static void evm_nand_init(int evm_id, int profile){    struct omap_nand_platform_data *pdata;    struct gpmc_devices_info gpmc_device[2] = {        { NULL, 0 },        { NULL, 0 },    };    setup_pin_mux(nand_pin_mux);    pdata = omap_nand_init(am335x_nand_partitions,        ARRAY_SIZE(am335x_nand_partitions), 0, 0,        &am335x_nand_timings);    if (!pdata)        return;    //pdata->xfer_type = NAND_OMAP_PREFETCH_DMA;    pdata->ecc_opt = OMAP_ECC_BCH8_CODE_HW;    tq335x_nand_config(pdata);    pdata->elm_used = true;    gpmc_device[0].pdata = pdata;    gpmc_device[0].flag = GPMC_DEVICE_NAND;    omap_init_gpmc(gpmc_device, sizeof(gpmc_device));    omap_init_elm();}

NAND_OMAP_PREFETCH_DMA 我加了这个内核就无法启动了。

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