TI中文支持网现在已经在内核中设置了阈值，各中断的优先级，如下：
intc_bank_write_reg(100, bank, INTC_THRESHOLD); //INTC_THRESHOLD
intc_bank_write_reg(4 << 2, bank, INTC_ILR0 + 62*4); //gpio3
intc_bank_write_reg(6 << 2, bank, INTC_ILR0 + 63*4); //gpio3
intc_bank_write_reg(6 << 2, bank, INTC_ILR0 + 63*4); //gpio3
intc_bank_write_reg(8 << 2, bank, INTC_ILR0 + 93*4); //eth网络中断
intc_bank_write_reg(8 << 2, bank, INTC_ILR0 + 94*4); //eth
intc_bank_write_reg(8 << 2, bank, INTC_ILR0 + 94*4); //eth
intc_bank_write_reg(10 << 2, bank, INTC_ILR0 + 68*4); //timer
intc_bank_write_reg(12 << 2, bank, INTC_ILR0 + 73*4); //uart1
intc_bank_write_reg(12 << 2, bank, INTC_ILR0 + 73*4); //uart1
intc_bank_write_reg(14 << 2, bank, INTC_ILR0 + 72*4); //uart0
测试的时候发现，执行网络中断的时候，gpio3中断还是切不进来。
按照datasheet中说法是在ISR中设置
6.2.4 Interrupt Preemption
If wanting to enable pre-emption by higher priority interrupts, the ISR should read the active interrupt
priority and write it to the priority threshold register. Writing a ‘1’ to the appropriate NEW_IRQ_AGR or
NEW_FIQ_AGR bits of the CONTROL register while still processing the interrupt will now allow only
higher priority interrupts to pre-empt.
If wanting to enable pre-emption by higher priority interrupts, the ISR should read the active interrupt
priority and write it to the priority threshold register. Writing a ‘1’ to the appropriate NEW_IRQ_AGR or
NEW_FIQ_AGR bits of the CONTROL register while still processing the interrupt will now allow only
higher priority interrupts to pre-empt.
但是：
6.2.3 INTC Preemptive Processing Sequence
Preemptive interrupts, also called nested interrupts, can reduce the latencies for higher priority interrupts.
A preemptive ISR can be suspended by a higher priority interrupt. Thus, the higher priority interrupt can be
served immediately. Nested interrupts must be used carefully to avoid using corrupted data. Programmers
must save corruptible registers and enable IRQ or FIQ at ARM side. IRQ and FIQ processing sequences
are quite similar, the differences for the FIQ sequence are shown after a '/' character in the code below.
To enable IRQ/FIQ preemption by higher priority IRQs/FIQs, programers can follow this procedure to write
the ISR.
At the beginning of an IRQ/FIQ ISR:
1. Save the ARM critical context registers.
2. Save the INTC_THRESHOLD PRIORITYTHRESHOLD field before modifying it.
3. Read the active interrupt priority in the INTC_IRQ_PRIORITY IRQPRIORITY/INTC_FIQ_PRIORITY
FIQPRIORITY field and write it to the PRIORITYTHRESHOLD(1) field.
4. Read the active interrupt number in the INTC_SIR_IRQ[6:0] ACTIVEIRQ/INTC_SIR_FIQ[6:0]
ACTIVEFIQ field to identify the interrupt source.
5. Write 1 to the appropriate INTC_CONTROL NEWIRQAGR and (2) NEWFIQAGR bit while an interrupt
is still processing to allow only higher priority interrupts to preempt.
6. Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are done
before enabling IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the IRQ
line is de-asserted before IRQ/FIQ enabling.
7. Enable IRQ/FIQ at ARM side.
8. Jump to the relevant subroutine handler.
Preemptive interrupts, also called nested interrupts, can reduce the latencies for higher priority interrupts.
A preemptive ISR can be suspended by a higher priority interrupt. Thus, the higher priority interrupt can be
served immediately. Nested interrupts must be used carefully to avoid using corrupted data. Programmers
must save corruptible registers and enable IRQ or FIQ at ARM side. IRQ and FIQ processing sequences
are quite similar, the differences for the FIQ sequence are shown after a '/' character in the code below.
To enable IRQ/FIQ preemption by higher priority IRQs/FIQs, programers can follow this procedure to write
the ISR.
At the beginning of an IRQ/FIQ ISR:
1. Save the ARM critical context registers.
2. Save the INTC_THRESHOLD PRIORITYTHRESHOLD field before modifying it.
3. Read the active interrupt priority in the INTC_IRQ_PRIORITY IRQPRIORITY/INTC_FIQ_PRIORITY
FIQPRIORITY field and write it to the PRIORITYTHRESHOLD(1) field.
4. Read the active interrupt number in the INTC_SIR_IRQ[6:0] ACTIVEIRQ/INTC_SIR_FIQ[6:0]
ACTIVEFIQ field to identify the interrupt source.
5. Write 1 to the appropriate INTC_CONTROL NEWIRQAGR and (2) NEWFIQAGR bit while an interrupt
is still processing to allow only higher priority interrupts to preempt.
6. Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are done
before enabling IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the IRQ
line is de-asserted before IRQ/FIQ enabling.
7. Enable IRQ/FIQ at ARM side.
8. Jump to the relevant subroutine handler.
这里面又是在设置之后才进入了中断处理程序！！！
不知道该怎样操作，希望大家帮忙看看，怎样处理？谢谢！
yongqing wang：
看看这个帖子：blog.csdn.net/…/73473449
