TI中文支持网hi,
自己的设计的开发板，使用dm6446芯片，没有使用AD芯片，输入直接从fpga接dsp 的vpfe,bt656的格式，fpga的数据pin0-pin7 连接vpfe的ccd0-ccd7,clk连接vpfe的pclk，现在的问题是，我直接使用ti提供的demo,vga_loop,屏蔽初始化ad函数无法capture到fpga的输入过来的数据。
fpga的输入数据和时钟都已经用示波器测试确定都正确，请问我还需要设置什么呢？
我的vpfe配置如下：
void vpfe_init( Uint32 buffer, Uint32 width, Uint32 height,Uint8 channel )
{
VPFE_SYN_MODE = 0x00032F87; // interlaced, with VD pority as negative
VPFE_HD_VD_WID = 0;
VPFE_PIX_LINES = 0; //linger 720×624
/*
* sph = 1, nph = 1440, according to page 32-33 of the CCDC spec
* for BT.656 mode, this setting captures only the 720×480 of the
* active NTSV video window
*/
VPFE_HORZ_INFO = width << 1; // Horizontal lines
VPFE_HSIZE_OFF = width << 1; // Horizontal line offset
VPFE_VERT_START = 0; // Vertical start line
VPFE_VERT_LINES = height >> 1; // Vertical lines
VPFE_CULLING = 0xFFFF00FF; // Disable cullng
/*
* Interleave the two fields */
VPFE_SDOFST = 0x00000249;
VPFE_SDR_ADDR = buffer;
VPFE_CLAMP = 0;
VPFE_DCSUB = 0;
VPFE_COLPTN = 0xEE44EE44;
VPFE_BLKCMP = 0;
VPFE_FPC_ADDR = 0x86800000;
VPFE_FPC = 0;
VPFE_VDINT = 0;
VPFE_ALAW = 0;
VPFE_REC656IF = 0x00000003;
/*
* Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position */
VPFE_CCDCFG = 0x00008800;//800
VPFE_FMTCFG = 0x00008000; //linger//0
VPFE_FMT_HORZ = 0x000002D0;
VPFE_FMT_VERT = 0x00000240;//0x00000272;
VPFE_FMT_ADDR0 = 0;
VPFE_FMT_ADDR1 = 0;
VPFE_FMT_ADDR2 = 0;
VPFE_FMT_ADDR3 = 0;
VPFE_FMT_ADDR4 = 0;
VPFE_FMT_ADDR5 = 0;
VPFE_FMT_ADDR6 = 0;
VPFE_FMT_ADDR7 = 0;
VPFE_PRGEVEN_0 = 0;
VPFE_PRGEVEN_1 = 0;
VPFE_PRGODD_0 = 0;
VPFE_PRGODD_1 = 0;
VPFE_VP_OUT = 0x04E22D00;//41a2d00
VPFE_PCR = 0x00000001; // Enable CCDC
}
Chris Meng：
你好，
由于你配置的是BT656，是内嵌同步的，你输出的数据里面必须有正确的SAV/EAV，DM6446才能解析到同步信号进行采集。你能确认SAV/EAV从FPGA输出是正确的么?
