TI中文支持网8148芯片，跑的是8127 appro ipnc rdk 3.5的包，psp版本是04.04.00.02
我们使用其中一个脚用于rs485的片选cs脚，想复用为gpio输出。但是怎么搞都无法其作用，该脚一直为高电平..gpio无法控制它变低，所以485只能发送，接收不了。
代码我放到了/home/tracyone/work/dm8127/Source/ti_tools/ipnc_psp_arago/kernel/arch/arm/mach-omap2/devices.c
中的omap2_init_devices(void)的最后…该函数看起来应该是内核对管脚进行复用设置的顶层函数..所以放在最后应该能保证不被重写
omap_mux_init_signal("uart0_dcdn.gpio1_2", 0);
/*omap_writel(0x80, 0x48140924);*/
error = gpio_request(34, "rs485");
if (error) {
printk(KERN_ERR "%s: failed to request GPIO for rs485_cs"
": %d\n", __func__, error);
return;
}
gpio_direction_output(34,0); /*默认接收状态*/
gpio_export(34, true);
然后我有又全局搜索下面这个宏定义所有复用模式，确保没被重写
_TI814X_MUXENTRY(UART0_DCDN, 0,
"uart0_dcdn", "uart3_rxd_mux0", NULL, NULL, "spi0_cs3",
"i2c2_scl_mux0", "mmc1_pow", "gpio1_2", NULL, NULL,
NULL, NULL),
结果还是无法控制该GPIO，求思路！！
Eason Wang：
Hi，那你是否有回读过PINCTRL寄存器看这个管脚最终是被配置成什么功能？如果读出来的确不是GPIO的话，还得找找哪里给覆盖了。
peng cheng2：
个人感觉，485读写时，对gpio的高低设置，应该加上一点延时。
大白他弟：
回复 Eason Wang:
你好，请问下能在应用层回读这个寄存器的值么？如何？
Louis：
回复 Eason Wang:
能否使用CCS配合以下GEL脚本来确保硬件工作正常？
#define PRCM_BASE_ADDR 0x48180000
#define MCBSP_BASE_ADDR 0x47000000
//GP0[1] Y6 R228
#define WR_MEM_32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)#define RD_MEM_32(addr) *(unsigned int*)(addr)
hotmenu GPIO_ClkEnable(){
#define CM_ALWON_GPIO_0_CLKCTRL (PRCM_BASE_ADDR + 0x155C)
#define CM_ALWON_GPIO_1_CLKCTRL (PRCM_BASE_ADDR + 0x1560)
WR_MEM_32(CM_ALWON_GPIO_0_CLKCTRL, 0x2); /* Enable GPI0 System and Functional Clock*/
while(RD_MEM_32(CM_ALWON_GPIO_0_CLKCTRL)!=0x2); /* Poll till Module is functional*/
WR_MEM_32(CM_ALWON_GPIO_1_CLKCTRL, 0x2); /* Enable GPI1 System and Functional Clock*/
while(RD_MEM_32(CM_ALWON_GPIO_1_CLKCTRL)!=0x2); /* Poll till Module is functional*/
GEL_TextOut("\tGPIO 0&1 clock is enalbed successfully !!!\n");
}
hotmenu GPIO1_EnableLvcmosPadN_PadPReceiver(){
#define MLBP_SIG_IO_CTRL_FOR_GPb7b8 0x48140E18#define MLBP_SIG_IO_CTRL_FOR_GPb9b10 0x48140E1c
#define MLBP_SIG_IO_CTRL_VAL 0x3F //set 3LSB to enable: 2 lvcmos buffer, padn receiver, padp receiver
WR_MEM_32(MLBP_SIG_IO_CTRL_FOR_GPb7b8, MLBP_SIG_IO_CTRL_VAL); WR_MEM_32(MLBP_SIG_IO_CTRL_FOR_GPb9b10, MLBP_SIG_IO_CTRL_VAL); }
hotmenu GPIO_SelectGPIO_0and1_Pinmux(){//for GP1#define PINCNTL62 0x481408F4#define PINCNTL63 0x481408F8#define PINCNTL64 0x481408FC#define PINCNTL65 0x48140900
//for GP0#define PINCNTL8 0x4814081C
#define MUX_VAL 0x00040080 WR_MEM_32(PINCNTL62, MUX_VAL); WR_MEM_32(PINCNTL63, MUX_VAL); WR_MEM_32(PINCNTL64, MUX_VAL); WR_MEM_32(PINCNTL65, MUX_VAL);
WR_MEM_32(PINCNTL8, 0x00040080); } hotmenu GPIO_SelectGPIO1_bit7_to_W6_Pinmux(){//for GP1, check R143#define PINCNTL07 0x48140818
WR_MEM_32(PINCNTL07, 0x00040080);
} hotmenu GPIO1_OutputEnable_High(){
#define GPIO1_OE 0x4804C134#define GPIO1_SETDATAOUT 0x4804C194#define GPIO1_DATAOUT 0x4804C13C
WR_MEM_32(GPIO1_OE, 0); WR_MEM_32(GPIO1_SETDATAOUT, 0xffffffff); }
hotmenu GPIO1_OutputEnable_Low(){
#define GPIO1_OE 0x4804C134#define GPIO1_SETDATAOUT 0x4804C194#define GPIO1_DATAOUT 0x4804C13C
WR_MEM_32(GPIO1_OE, 0); WR_MEM_32(GPIO1_DATAOUT, 0); }
hotmenu GPIO0_OutputEnable_High(){
#define GPIO0_OE 0x48032134#define GPIO0_SETDATAOUT 0x48032194#define GPIO0_DATAOUT 0x4803213C
WR_MEM_32(GPIO0_OE, 0); WR_MEM_32(GPIO0_SETDATAOUT, 0x2); }
hotmenu GPIO0_OutputEnable_Low(){
#define GPIO0_OE 0x48032134#define GPIO0_SETDATAOUT 0x48032194#define GPIO0_DATAOUT 0x4803213C
WR_MEM_32(GPIO0_OE, 0); WR_MEM_32(GPIO0_DATAOUT, 0); }
