TI中文支持网大家好，我正在用F28027的开发板制作 闭环控制回路。我用 DPL的 2p2z, ADC, Epwm，来进行闭环控制。
一切链接的非常顺利，也可以正常的闭环控制，2p2z非常精确的控制pid。
但是，如果我不能增加任意一条 变量声明，例如 long test；在 {ProjectName}-main.c 文件的 main() 文件头处。
如果加入了一条以上的变量，2p2z的输出变得不可控，也就是说，无论反馈端是什么，out都不变。
不知道这是linker的问题还是别的问题？我尝试更改RAM linker, .ebss 的地址，或者 dataRAM的地址或者长度，结果没有任何变化。
下面是我的linker 文件的内容：
/*==================================================================================*/
/* User specific Linker command file for running from RAM*/
/*==================================================================================*/
/* FILE:F28027_RAM_ProjectName.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/*from RAM. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version:1.1 */
/* */
/*———————————————————————————-*/
/* Copyright Texas Instruments ? 2007 */
/*———————————————————————————-*/
/* Revision History: */
/*———————————————————————————-*/
/* Date | Description */
/*———————————————————————————-*/
/* 04/23/09 | Release 1.1 */
/*———————————————————————————-*/
/* Define the memory block start/length for the DSP2802x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28022 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory blocks is mirrored – that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x000000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x00004E
RAMM0 : origin = 0x000050, length = 0x0003B0
progRAM : origin = 0x008000, length = 0x000800
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000480, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
ramfuncs : > progRAM, PAGE = 0
.text : > progRAM, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0,TYPE =DSECT
.stack : > RAMM1, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.econst : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > progRAM, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0,TYPE =NOLOAD
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ADCDRV_1ch section */
ADCDRV_1ch_Section: > dataRAMPAGE = 1
/* ADCDRV_4ch section */
ADCDRV_8ch_Section: > dataRAMPAGE = 1
/* CNTL_2P2Z section */
CNTL_2P2Z_Section: > dataRAMPAGE = 1
CNTL_2P2Z_InternalData: > dataRAMPAGE = 1
CNTL_2P2Z_Coef: > dataRAMPAGE = 1
/* CNTL_3P3Z section */
CNTL_3P3Z_Section: > dataRAMPAGE = 1
CNTL_3P3Z_InternalData: > dataRAMPAGE = 1
CNTL_3P3Z_Coef: > dataRAMPAGE = 1
/*DLOG_4CH section */
DLOG_4CH_Section: > dataRAMPAGE = 1
DLOG_BUFF: > dataRAMPAGE = 1
/*MATH_EMAVG section */
MATH_EMAVG_Section: > dataRAMPAGE = 1
/*PFC_ICMD section*/
PFC_ICMD_Section: > dataRAMPAGE = 1
/*PFC_INVSQR section*/
PFC_INVSQR_Section: > dataRAMPAGE = 1
/* PWMDRV_1ch driver section */
PWMDRV_1ch_Section: > dataRAMPAGE = 1
/* PWMDRV_1chHiRes driver section */
PWMDRV_1chHiRes_Section: > dataRAMPAGE = 1
/* PWMDRV_PFC2PhiL driver section */
PWMDRV_PFC2PhiL_Section: > dataRAMPAGE = 1
/* PWMDRV_PSFB driver section */
PWMDRV_PSFB_Section: > dataRAMPAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */
PWMDRV_DualUpDwnCnt_Section : > dataRAMPAGE = 1
/* PWMDRV_ComplPairDB driver section */
PWMDRV_ComplPairDB_Section : > dataRAMPAGE = 1
/* ZeroNet_Section */
ZeroNet_Section: > dataRAMPAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Taisen Zhuang：
我也尝试用F28069的芯片进行尝试，问题非常类似，2p2z变得不可控。
大家好，我正在用F28027的开发板制作 闭环控制回路。我用 DPL的 2p2z, ADC, Epwm，来进行闭环控制。
一切链接的非常顺利，也可以正常的闭环控制，2p2z非常精确的控制pid。
但是，如果我不能增加任意一条 变量声明，例如 long test；在 {ProjectName}-main.c 文件的 main() 文件头处。
如果加入了一条以上的变量，2p2z的输出变得不可控，也就是说，无论反馈端是什么，out都不变。
不知道这是linker的问题还是别的问题？我尝试更改RAM linker, .ebss 的地址，或者 dataRAM的地址或者长度，结果没有任何变化。
下面是我的linker 文件的内容：
/*==================================================================================*/
/* User specific Linker command file for running from RAM*/
/*==================================================================================*/
/* FILE:F28027_RAM_ProjectName.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/*from RAM. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version:1.1 */
/* */
/*———————————————————————————-*/
/* Copyright Texas Instruments ? 2007 */
/*———————————————————————————-*/
/* Revision History: */
/*———————————————————————————-*/
/* Date | Description */
/*———————————————————————————-*/
/* 04/23/09 | Release 1.1 */
/*———————————————————————————-*/
/* Define the memory block start/length for the DSP2802x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28022 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory blocks is mirrored – that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x000000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x00004E
RAMM0 : origin = 0x000050, length = 0x0003B0
progRAM : origin = 0x008000, length = 0x000800
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000480, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
ramfuncs : > progRAM, PAGE = 0
.text : > progRAM, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0,TYPE =DSECT
.stack : > RAMM1, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.econst : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > progRAM, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0,TYPE =NOLOAD
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ADCDRV_1ch section */
ADCDRV_1ch_Section: > dataRAMPAGE = 1
/* ADCDRV_4ch section */
ADCDRV_8ch_Section: > dataRAMPAGE = 1
/* CNTL_2P2Z section */
CNTL_2P2Z_Section: > dataRAMPAGE = 1
CNTL_2P2Z_InternalData: > dataRAMPAGE = 1
CNTL_2P2Z_Coef: > dataRAMPAGE = 1
/* CNTL_3P3Z section */
CNTL_3P3Z_Section: > dataRAMPAGE = 1
CNTL_3P3Z_InternalData: > dataRAMPAGE = 1
CNTL_3P3Z_Coef: > dataRAMPAGE = 1
/*DLOG_4CH section */
DLOG_4CH_Section: > dataRAMPAGE = 1
DLOG_BUFF: > dataRAMPAGE = 1
/*MATH_EMAVG section */
MATH_EMAVG_Section: > dataRAMPAGE = 1
/*PFC_ICMD section*/
PFC_ICMD_Section: > dataRAMPAGE = 1
/*PFC_INVSQR section*/
PFC_INVSQR_Section: > dataRAMPAGE = 1
/* PWMDRV_1ch driver section */
PWMDRV_1ch_Section: > dataRAMPAGE = 1
/* PWMDRV_1chHiRes driver section */
PWMDRV_1chHiRes_Section: > dataRAMPAGE = 1
/* PWMDRV_PFC2PhiL driver section */
PWMDRV_PFC2PhiL_Section: > dataRAMPAGE = 1
/* PWMDRV_PSFB driver section */
PWMDRV_PSFB_Section: > dataRAMPAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */
PWMDRV_DualUpDwnCnt_Section : > dataRAMPAGE = 1
/* PWMDRV_ComplPairDB driver section */
PWMDRV_ComplPairDB_Section : > dataRAMPAGE = 1
/* ZeroNet_Section */
ZeroNet_Section: > dataRAMPAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
q l：
请问下2P2Z的参数是怎么设置的啊
大家好，我正在用F28027的开发板制作 闭环控制回路。我用 DPL的 2p2z, ADC, Epwm，来进行闭环控制。
一切链接的非常顺利，也可以正常的闭环控制，2p2z非常精确的控制pid。
但是，如果我不能增加任意一条 变量声明，例如 long test；在 {ProjectName}-main.c 文件的 main() 文件头处。
如果加入了一条以上的变量，2p2z的输出变得不可控，也就是说，无论反馈端是什么，out都不变。
不知道这是linker的问题还是别的问题？我尝试更改RAM linker, .ebss 的地址，或者 dataRAM的地址或者长度，结果没有任何变化。
下面是我的linker 文件的内容：
/*==================================================================================*/
/* User specific Linker command file for running from RAM*/
/*==================================================================================*/
/* FILE:F28027_RAM_ProjectName.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/*from RAM. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version:1.1 */
/* */
/*———————————————————————————-*/
/* Copyright Texas Instruments ? 2007 */
/*———————————————————————————-*/
/* Revision History: */
/*———————————————————————————-*/
/* Date | Description */
/*———————————————————————————-*/
/* 04/23/09 | Release 1.1 */
/*———————————————————————————-*/
/* Define the memory block start/length for the DSP2802x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28022 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory blocks is mirrored – that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x000000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x00004E
RAMM0 : origin = 0x000050, length = 0x0003B0
progRAM : origin = 0x008000, length = 0x000800
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000480, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
ramfuncs : > progRAM, PAGE = 0
.text : > progRAM, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0,TYPE =DSECT
.stack : > RAMM1, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.econst : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > progRAM, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0,TYPE =NOLOAD
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ADCDRV_1ch section */
ADCDRV_1ch_Section: > dataRAMPAGE = 1
/* ADCDRV_4ch section */
ADCDRV_8ch_Section: > dataRAMPAGE = 1
/* CNTL_2P2Z section */
CNTL_2P2Z_Section: > dataRAMPAGE = 1
CNTL_2P2Z_InternalData: > dataRAMPAGE = 1
CNTL_2P2Z_Coef: > dataRAMPAGE = 1
/* CNTL_3P3Z section */
CNTL_3P3Z_Section: > dataRAMPAGE = 1
CNTL_3P3Z_InternalData: > dataRAMPAGE = 1
CNTL_3P3Z_Coef: > dataRAMPAGE = 1
/*DLOG_4CH section */
DLOG_4CH_Section: > dataRAMPAGE = 1
DLOG_BUFF: > dataRAMPAGE = 1
/*MATH_EMAVG section */
MATH_EMAVG_Section: > dataRAMPAGE = 1
/*PFC_ICMD section*/
PFC_ICMD_Section: > dataRAMPAGE = 1
/*PFC_INVSQR section*/
PFC_INVSQR_Section: > dataRAMPAGE = 1
/* PWMDRV_1ch driver section */
PWMDRV_1ch_Section: > dataRAMPAGE = 1
/* PWMDRV_1chHiRes driver section */
PWMDRV_1chHiRes_Section: > dataRAMPAGE = 1
/* PWMDRV_PFC2PhiL driver section */
PWMDRV_PFC2PhiL_Section: > dataRAMPAGE = 1
/* PWMDRV_PSFB driver section */
PWMDRV_PSFB_Section: > dataRAMPAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */
PWMDRV_DualUpDwnCnt_Section : > dataRAMPAGE = 1
/* PWMDRV_ComplPairDB driver section */
PWMDRV_ComplPairDB_Section : > dataRAMPAGE = 1
/* ZeroNet_Section */
ZeroNet_Section: > dataRAMPAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Taisen Zhuang：
回复 q l:
// Connect the CNTL_2P2Z block to the variables
CNTL_2P2Z_Fdbk1 = &RltA; //Q24 [0, 1)
CNTL_2P2Z_Out1 = &Out; //Q24 [0, 1)
CNTL_2P2Z_Ref1 = &Ref; //Q24 [0, 1)
CNTL_2P2Z_Coef1 = &CNTL_2P2Z_CoefStruct1.b2;
// Coefficients for the Voltage Loop
// PID coefficients & Clamping (Q26)
Dmax = _IQ24(0.984375); //Q24
Dmin = _IQ24(0.0); //Q24
Pgain = _IQ26(0.001953); //Q26
Igain = _IQ26(0.001250); //Q26
Dgain = _IQ26(0.0); //Q26
// Coefficient init — Coeeficient values in Q26
// Use IQ Maths to generate floating point values for the CLA
CNTL_2P2Z_CoefStruct1.b2 = Dgain; // B2
CNTL_2P2Z_CoefStruct1.b1 = (Igain-Pgain-Dgain-Dgain); // B1
CNTL_2P2Z_CoefStruct1.b0 = (Pgain + Igain + Dgain); // B0
CNTL_2P2Z_CoefStruct1.a2 = 0.0; // A2 = 0
CNTL_2P2Z_CoefStruct1.a1 = _IQ26(1.0); // A1 = 1
CNTL_2P2Z_CoefStruct1.max = Dmax; //Clamp Hi
CNTL_2P2Z_CoefStruct1.min = Dmin; //Clamp Min
2p2z的Node链接到了ADC，我用了ADCDRV8ch的，用Epwm1来驱动INT，用2p2z的out来驱动Epwm的Duty口。
大家好，我正在用F28027的开发板制作 闭环控制回路。我用 DPL的 2p2z, ADC, Epwm，来进行闭环控制。
一切链接的非常顺利，也可以正常的闭环控制，2p2z非常精确的控制pid。
但是，如果我不能增加任意一条 变量声明，例如 long test；在 {ProjectName}-main.c 文件的 main() 文件头处。
如果加入了一条以上的变量，2p2z的输出变得不可控，也就是说，无论反馈端是什么，out都不变。
不知道这是linker的问题还是别的问题？我尝试更改RAM linker, .ebss 的地址，或者 dataRAM的地址或者长度，结果没有任何变化。
下面是我的linker 文件的内容：
/*==================================================================================*/
/* User specific Linker command file for running from RAM*/
/*==================================================================================*/
/* FILE:F28027_RAM_ProjectName.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/*from RAM. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version:1.1 */
/* */
/*———————————————————————————-*/
/* Copyright Texas Instruments ? 2007 */
/*———————————————————————————-*/
/* Revision History: */
/*———————————————————————————-*/
/* Date | Description */
/*———————————————————————————-*/
/* 04/23/09 | Release 1.1 */
/*———————————————————————————-*/
/* Define the memory block start/length for the DSP2802x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28022 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory blocks is mirrored – that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x000000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x00004E
RAMM0 : origin = 0x000050, length = 0x0003B0
progRAM : origin = 0x008000, length = 0x000800
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000480, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
ramfuncs : > progRAM, PAGE = 0
.text : > progRAM, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0,TYPE =DSECT
.stack : > RAMM1, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.econst : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > progRAM, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0,TYPE =NOLOAD
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ADCDRV_1ch section */
ADCDRV_1ch_Section: > dataRAMPAGE = 1
/* ADCDRV_4ch section */
ADCDRV_8ch_Section: > dataRAMPAGE = 1
/* CNTL_2P2Z section */
CNTL_2P2Z_Section: > dataRAMPAGE = 1
CNTL_2P2Z_InternalData: > dataRAMPAGE = 1
CNTL_2P2Z_Coef: > dataRAMPAGE = 1
/* CNTL_3P3Z section */
CNTL_3P3Z_Section: > dataRAMPAGE = 1
CNTL_3P3Z_InternalData: > dataRAMPAGE = 1
CNTL_3P3Z_Coef: > dataRAMPAGE = 1
/*DLOG_4CH section */
DLOG_4CH_Section: > dataRAMPAGE = 1
DLOG_BUFF: > dataRAMPAGE = 1
/*MATH_EMAVG section */
MATH_EMAVG_Section: > dataRAMPAGE = 1
/*PFC_ICMD section*/
PFC_ICMD_Section: > dataRAMPAGE = 1
/*PFC_INVSQR section*/
PFC_INVSQR_Section: > dataRAMPAGE = 1
/* PWMDRV_1ch driver section */
PWMDRV_1ch_Section: > dataRAMPAGE = 1
/* PWMDRV_1chHiRes driver section */
PWMDRV_1chHiRes_Section: > dataRAMPAGE = 1
/* PWMDRV_PFC2PhiL driver section */
PWMDRV_PFC2PhiL_Section: > dataRAMPAGE = 1
/* PWMDRV_PSFB driver section */
PWMDRV_PSFB_Section: > dataRAMPAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */
PWMDRV_DualUpDwnCnt_Section : > dataRAMPAGE = 1
/* PWMDRV_ComplPairDB driver section */
PWMDRV_ComplPairDB_Section : > dataRAMPAGE = 1
/* ZeroNet_Section */
ZeroNet_Section: > dataRAMPAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
david guo1：
回复 Taisen Zhuang:
我也遇到同样问题，真是奇怪。编译都是好好的，没有提示任何数据越界什么的，但是PID环路就是不启动。
大家好，我正在用F28027的开发板制作 闭环控制回路。我用 DPL的 2p2z, ADC, Epwm，来进行闭环控制。
一切链接的非常顺利，也可以正常的闭环控制，2p2z非常精确的控制pid。
但是，如果我不能增加任意一条 变量声明，例如 long test；在 {ProjectName}-main.c 文件的 main() 文件头处。
如果加入了一条以上的变量，2p2z的输出变得不可控，也就是说，无论反馈端是什么，out都不变。
不知道这是linker的问题还是别的问题？我尝试更改RAM linker, .ebss 的地址，或者 dataRAM的地址或者长度，结果没有任何变化。
下面是我的linker 文件的内容：
/*==================================================================================*/
/* User specific Linker command file for running from RAM*/
/*==================================================================================*/
/* FILE:F28027_RAM_ProjectName.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/*from RAM. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version:1.1 */
/* */
/*———————————————————————————-*/
/* Copyright Texas Instruments ? 2007 */
/*———————————————————————————-*/
/* Revision History: */
/*———————————————————————————-*/
/* Date | Description */
/*———————————————————————————-*/
/* 04/23/09 | Release 1.1 */
/*———————————————————————————-*/
/* Define the memory block start/length for the DSP2802x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28022 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory blocks is mirrored – that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x000000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x00004E
RAMM0 : origin = 0x000050, length = 0x0003B0
progRAM : origin = 0x008000, length = 0x000800
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000480, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
ramfuncs : > progRAM, PAGE = 0
.text : > progRAM, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0,TYPE =DSECT
.stack : > RAMM1, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.econst : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > progRAM, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0,TYPE =NOLOAD
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ADCDRV_1ch section */
ADCDRV_1ch_Section: > dataRAMPAGE = 1
/* ADCDRV_4ch section */
ADCDRV_8ch_Section: > dataRAMPAGE = 1
/* CNTL_2P2Z section */
CNTL_2P2Z_Section: > dataRAMPAGE = 1
CNTL_2P2Z_InternalData: > dataRAMPAGE = 1
CNTL_2P2Z_Coef: > dataRAMPAGE = 1
/* CNTL_3P3Z section */
CNTL_3P3Z_Section: > dataRAMPAGE = 1
CNTL_3P3Z_InternalData: > dataRAMPAGE = 1
CNTL_3P3Z_Coef: > dataRAMPAGE = 1
/*DLOG_4CH section */
DLOG_4CH_Section: > dataRAMPAGE = 1
DLOG_BUFF: > dataRAMPAGE = 1
/*MATH_EMAVG section */
MATH_EMAVG_Section: > dataRAMPAGE = 1
/*PFC_ICMD section*/
PFC_ICMD_Section: > dataRAMPAGE = 1
/*PFC_INVSQR section*/
PFC_INVSQR_Section: > dataRAMPAGE = 1
/* PWMDRV_1ch driver section */
PWMDRV_1ch_Section: > dataRAMPAGE = 1
/* PWMDRV_1chHiRes driver section */
PWMDRV_1chHiRes_Section: > dataRAMPAGE = 1
/* PWMDRV_PFC2PhiL driver section */
PWMDRV_PFC2PhiL_Section: > dataRAMPAGE = 1
/* PWMDRV_PSFB driver section */
PWMDRV_PSFB_Section: > dataRAMPAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */
PWMDRV_DualUpDwnCnt_Section : > dataRAMPAGE = 1
/* PWMDRV_ComplPairDB driver section */
PWMDRV_ComplPairDB_Section : > dataRAMPAGE = 1
/* ZeroNet_Section */
ZeroNet_Section: > dataRAMPAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
david guo1：
经验证，2p2z的参数设置中需要多增加一个 CNTL_2P2Z_CoefStruct1.i_min = _IQ24(-0.98); 这样能够使得2p2z运算稳定。
而不是像楼主所说的那个样子。我在实际应用中遇到了同样的问题，困扰了我很久，最后在读Ti的例子时关注到了这个参数，
经验证加了这个参数后运算就稳定了。因此希望更多人看到这个帖子，同时可以帮到更多的人。
大家好，我正在用F28027的开发板制作 闭环控制回路。我用 DPL的 2p2z, ADC, Epwm，来进行闭环控制。
一切链接的非常顺利，也可以正常的闭环控制，2p2z非常精确的控制pid。
但是，如果我不能增加任意一条 变量声明，例如 long test；在 {ProjectName}-main.c 文件的 main() 文件头处。
如果加入了一条以上的变量，2p2z的输出变得不可控，也就是说，无论反馈端是什么，out都不变。
不知道这是linker的问题还是别的问题？我尝试更改RAM linker, .ebss 的地址，或者 dataRAM的地址或者长度，结果没有任何变化。
下面是我的linker 文件的内容：
/*==================================================================================*/
/* User specific Linker command file for running from RAM*/
/*==================================================================================*/
/* FILE:F28027_RAM_ProjectName.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/*from RAM. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version:1.1 */
/* */
/*———————————————————————————-*/
/* Copyright Texas Instruments ? 2007 */
/*———————————————————————————-*/
/* Revision History: */
/*———————————————————————————-*/
/* Date | Description */
/*———————————————————————————-*/
/* 04/23/09 | Release 1.1 */
/*———————————————————————————-*/
/* Define the memory block start/length for the DSP2802x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28022 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory blocks is mirrored – that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x000000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x00004E
RAMM0 : origin = 0x000050, length = 0x0003B0
progRAM : origin = 0x008000, length = 0x000800
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000480, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
ramfuncs : > progRAM, PAGE = 0
.text : > progRAM, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0,TYPE =DSECT
.stack : > RAMM1, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.econst : > RAMM1, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > progRAM, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0,TYPE =NOLOAD
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ADCDRV_1ch section */
ADCDRV_1ch_Section: > dataRAMPAGE = 1
/* ADCDRV_4ch section */
ADCDRV_8ch_Section: > dataRAMPAGE = 1
/* CNTL_2P2Z section */
CNTL_2P2Z_Section: > dataRAMPAGE = 1
CNTL_2P2Z_InternalData: > dataRAMPAGE = 1
CNTL_2P2Z_Coef: > dataRAMPAGE = 1
/* CNTL_3P3Z section */
CNTL_3P3Z_Section: > dataRAMPAGE = 1
CNTL_3P3Z_InternalData: > dataRAMPAGE = 1
CNTL_3P3Z_Coef: > dataRAMPAGE = 1
/*DLOG_4CH section */
DLOG_4CH_Section: > dataRAMPAGE = 1
DLOG_BUFF: > dataRAMPAGE = 1
/*MATH_EMAVG section */
MATH_EMAVG_Section: > dataRAMPAGE = 1
/*PFC_ICMD section*/
PFC_ICMD_Section: > dataRAMPAGE = 1
/*PFC_INVSQR section*/
PFC_INVSQR_Section: > dataRAMPAGE = 1
/* PWMDRV_1ch driver section */
PWMDRV_1ch_Section: > dataRAMPAGE = 1
/* PWMDRV_1chHiRes driver section */
PWMDRV_1chHiRes_Section: > dataRAMPAGE = 1
/* PWMDRV_PFC2PhiL driver section */
PWMDRV_PFC2PhiL_Section: > dataRAMPAGE = 1
/* PWMDRV_PSFB driver section */
PWMDRV_PSFB_Section: > dataRAMPAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */
PWMDRV_DualUpDwnCnt_Section : > dataRAMPAGE = 1
/* PWMDRV_ComplPairDB driver section */
PWMDRV_ComplPairDB_Section : > dataRAMPAGE = 1
/* ZeroNet_Section */
ZeroNet_Section: > dataRAMPAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Taisen Zhuang：
回复 david guo1:
谢谢你的回复，我的问题已经解决了，是linker的内存设置问题。你说的在最小值处加上负数方法可能对稳定性有帮助，还没有尝试，可以去试试。
