TI中文支持网采用controlCard tms32028379d来实现EPWM变频输出，系统时钟200MHz, EPWM时钟100MHz. 相关代码如下：
if((fabs(EPwm2Regs.TBPRD – CRM_Ctrl.BPRD) < 40)&&(CRM_Ctrl.BPRD >= 99)&&(CRM_Ctrl.BPRD <= 500)&&(EPwm2Regs.TBPRD < CRM_Ctrl.BPRD))
{
Frequency_change_cnt++;
EALLOW;
GpioDataRegs.GPATOGGLE.bit.GPIO12 = 1;
EPwm2Regs.TBPRD = CRM_Ctrl.BPRD;
PI_TLBDC_I[0].d_s1 = CRM_Ctrl.New_Dton;
EDIS;
}
通过改变PWM2模块中寄存器EPwm2Regs.TBPRD来实现变频，发现在写TBPRD的时候，输出PWM2信号在一段时间内会被拉低或者拉高，持续时间在1ms左右，之后又恢复正常，变频范围在500kHz~1MHz, 尝试改变TBCTL.PRDLD发现问题依然存在。
PWM相关寄存器配置如下：
EPwm2Regs.TBPRD =199; //PWM period
EPwm2Regs.TBPHS.bit.TBPHS = 0;//TLBDC_PHASE(120.0f);//0; //No phase shift
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2; //Free run
// EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; //Counter up after synchronization
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;//TB_CTR_ZERO;//TB_SYNC_IN;//TB_CTR_ZERO; //Send synchronization signal when counter = 0
EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;//TB_SHADOW; //Using shadow register for PWM period
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;//TB_DISABLE;//TB_DISABLE; //Master, don't need load phase register
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//TB_COUNT_UPDOWN; //TB_COUNT_UP;//Up-down mode
EPwm2Regs.CMPA.bit.CMPA = 0;//TLBDC_CMPA(0.3);//cmpa=zkb*prd(s1),zkb=pi_out
EPwm2Regs.CMPB.bit.CMPB = 0;//TLBDC_CMPB(0.3);//phase=180; zkb'=pi_out,cmpb=(1-zkb')*prd=(1-pi_out)*prd (s2,pass a not logic->s3)
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;//Load new compare value when counter = period
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;//CC_CTR_ZERO;//Load new compare value when counter = zero
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;//AQ_SET; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; //AQ_CLEAR; // Clear PWM1A on event A,
// up count
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B,
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;//DBA_RED_DBB_FED;//DBB_RED_DBA_FED;//s5=1,s4=0
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//DBB_ENABLE;//DB_DISABLE;//DBB_ENABLE;// s1=0,s0=1(Q3)->0(Q2)
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;//DB_ACTV_LOC;//DB_ACTV_HI;//DB_ACTV_LO;//0x00;//DB_ACTV_HIC;// s3=1,s2=0->1, Active Hi complementary
EPwm2Regs.DBFED = 0x05;//INV_DEAD_CYCLE;// FED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBRED = 0x02;//INV_DEAD_CYCLE;// RED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBCTL.bit.OUTSWAP = 0x00;//0x03;
//add soca
EPwm2Regs.ETSEL.bit.SOCAEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCASEL=ET_CTR_PRDZERO;//ET_CTR_PRDZERO;
EPwm2Regs.ETPS.bit.SOCAPRD=ET_1ST;//divide frequency, page69/117.
EPwm2Regs.ETSEL.bit.SOCBEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCBSEL=ET_CTR_PRDZERO;//ET_CTR_ZERO;
EPwm2Regs.ETPS.bit.SOCBPRD=ET_1ST;//divide frequency
EPwm2Regs.ETSEL.bit.INTEN=ET_DISABLE;
EPwm2Regs.ETPS.bit.INTPRD=ET_DISABLE;
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TZ1; // DCAH = TZ1
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;//TZ_DCAH_LOW;//TZ_DCAL_HI_DCAH_LOW;
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; //DCAEVT1 =DCAEVT1(not filtered)
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;//DC_EVT_SYNC;//DC_EVT_ASYNC;//DC_EVT_SYNC;// // Take async path
EPwm2Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm2Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;//TZ_FORCE_LO; // EPWM1B will go low
EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm2Regs.DCACTL.bit.EVT1SYNCE = 1;
1.是有什么寄存器没有配置正确导致的吗，比如shadow register或者AQ之类的导致在写TBPRD的时候会被强制拉低或者拉高？
2.TI有没有相关的变频的例程啊 我找了很久都没找到？
Green Deng：你好，你设计的频率变化范围是多少？如果设置变化范围小一点还会有这种情况吗？例如从1MHz变为950kHz。
例程的话目前确实还没开发这类例程。
采用controlCard tms32028379d来实现EPWM变频输出，系统时钟200MHz, EPWM时钟100MHz. 相关代码如下：
if((fabs(EPwm2Regs.TBPRD – CRM_Ctrl.BPRD) < 40)&&(CRM_Ctrl.BPRD >= 99)&&(CRM_Ctrl.BPRD <= 500)&&(EPwm2Regs.TBPRD < CRM_Ctrl.BPRD))
{
Frequency_change_cnt++;
EALLOW;
GpioDataRegs.GPATOGGLE.bit.GPIO12 = 1;
EPwm2Regs.TBPRD = CRM_Ctrl.BPRD;
PI_TLBDC_I[0].d_s1 = CRM_Ctrl.New_Dton;
EDIS;
}
通过改变PWM2模块中寄存器EPwm2Regs.TBPRD来实现变频，发现在写TBPRD的时候，输出PWM2信号在一段时间内会被拉低或者拉高，持续时间在1ms左右，之后又恢复正常，变频范围在500kHz~1MHz, 尝试改变TBCTL.PRDLD发现问题依然存在。
PWM相关寄存器配置如下：
EPwm2Regs.TBPRD =199; //PWM period
EPwm2Regs.TBPHS.bit.TBPHS = 0;//TLBDC_PHASE(120.0f);//0; //No phase shift
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2; //Free run
// EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; //Counter up after synchronization
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;//TB_CTR_ZERO;//TB_SYNC_IN;//TB_CTR_ZERO; //Send synchronization signal when counter = 0
EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;//TB_SHADOW; //Using shadow register for PWM period
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;//TB_DISABLE;//TB_DISABLE; //Master, don't need load phase register
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//TB_COUNT_UPDOWN; //TB_COUNT_UP;//Up-down mode
EPwm2Regs.CMPA.bit.CMPA = 0;//TLBDC_CMPA(0.3);//cmpa=zkb*prd(s1),zkb=pi_out
EPwm2Regs.CMPB.bit.CMPB = 0;//TLBDC_CMPB(0.3);//phase=180; zkb'=pi_out,cmpb=(1-zkb')*prd=(1-pi_out)*prd (s2,pass a not logic->s3)
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;//Load new compare value when counter = period
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;//CC_CTR_ZERO;//Load new compare value when counter = zero
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;//AQ_SET; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; //AQ_CLEAR; // Clear PWM1A on event A,
// up count
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B,
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;//DBA_RED_DBB_FED;//DBB_RED_DBA_FED;//s5=1,s4=0
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//DBB_ENABLE;//DB_DISABLE;//DBB_ENABLE;// s1=0,s0=1(Q3)->0(Q2)
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;//DB_ACTV_LOC;//DB_ACTV_HI;//DB_ACTV_LO;//0x00;//DB_ACTV_HIC;// s3=1,s2=0->1, Active Hi complementary
EPwm2Regs.DBFED = 0x05;//INV_DEAD_CYCLE;// FED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBRED = 0x02;//INV_DEAD_CYCLE;// RED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBCTL.bit.OUTSWAP = 0x00;//0x03;
//add soca
EPwm2Regs.ETSEL.bit.SOCAEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCASEL=ET_CTR_PRDZERO;//ET_CTR_PRDZERO;
EPwm2Regs.ETPS.bit.SOCAPRD=ET_1ST;//divide frequency, page69/117.
EPwm2Regs.ETSEL.bit.SOCBEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCBSEL=ET_CTR_PRDZERO;//ET_CTR_ZERO;
EPwm2Regs.ETPS.bit.SOCBPRD=ET_1ST;//divide frequency
EPwm2Regs.ETSEL.bit.INTEN=ET_DISABLE;
EPwm2Regs.ETPS.bit.INTPRD=ET_DISABLE;
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TZ1; // DCAH = TZ1
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;//TZ_DCAH_LOW;//TZ_DCAL_HI_DCAH_LOW;
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; //DCAEVT1 =DCAEVT1(not filtered)
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;//DC_EVT_SYNC;//DC_EVT_ASYNC;//DC_EVT_SYNC;// // Take async path
EPwm2Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm2Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;//TZ_FORCE_LO; // EPWM1B will go low
EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm2Regs.DCACTL.bit.EVT1SYNCE = 1;
1.是有什么寄存器没有配置正确导致的吗，比如shadow register或者AQ之类的导致在写TBPRD的时候会被强制拉低或者拉高？
2.TI有没有相关的变频的例程啊 我找了很久都没找到？
mangui zhang：如果是周期出现的可能是寄存器等没有配置好如果是偶尔出现的建议你将输出管脚之后的负载去掉
只接示波器看看是否还出现这个问题
采用controlCard tms32028379d来实现EPWM变频输出，系统时钟200MHz, EPWM时钟100MHz. 相关代码如下：
if((fabs(EPwm2Regs.TBPRD – CRM_Ctrl.BPRD) < 40)&&(CRM_Ctrl.BPRD >= 99)&&(CRM_Ctrl.BPRD <= 500)&&(EPwm2Regs.TBPRD < CRM_Ctrl.BPRD))
{
Frequency_change_cnt++;
EALLOW;
GpioDataRegs.GPATOGGLE.bit.GPIO12 = 1;
EPwm2Regs.TBPRD = CRM_Ctrl.BPRD;
PI_TLBDC_I[0].d_s1 = CRM_Ctrl.New_Dton;
EDIS;
}
通过改变PWM2模块中寄存器EPwm2Regs.TBPRD来实现变频，发现在写TBPRD的时候，输出PWM2信号在一段时间内会被拉低或者拉高，持续时间在1ms左右，之后又恢复正常，变频范围在500kHz~1MHz, 尝试改变TBCTL.PRDLD发现问题依然存在。
PWM相关寄存器配置如下：
EPwm2Regs.TBPRD =199; //PWM period
EPwm2Regs.TBPHS.bit.TBPHS = 0;//TLBDC_PHASE(120.0f);//0; //No phase shift
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2; //Free run
// EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; //Counter up after synchronization
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;//TB_CTR_ZERO;//TB_SYNC_IN;//TB_CTR_ZERO; //Send synchronization signal when counter = 0
EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;//TB_SHADOW; //Using shadow register for PWM period
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;//TB_DISABLE;//TB_DISABLE; //Master, don't need load phase register
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//TB_COUNT_UPDOWN; //TB_COUNT_UP;//Up-down mode
EPwm2Regs.CMPA.bit.CMPA = 0;//TLBDC_CMPA(0.3);//cmpa=zkb*prd(s1),zkb=pi_out
EPwm2Regs.CMPB.bit.CMPB = 0;//TLBDC_CMPB(0.3);//phase=180; zkb'=pi_out,cmpb=(1-zkb')*prd=(1-pi_out)*prd (s2,pass a not logic->s3)
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;//Load new compare value when counter = period
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;//CC_CTR_ZERO;//Load new compare value when counter = zero
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;//AQ_SET; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; //AQ_CLEAR; // Clear PWM1A on event A,
// up count
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B,
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;//DBA_RED_DBB_FED;//DBB_RED_DBA_FED;//s5=1,s4=0
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//DBB_ENABLE;//DB_DISABLE;//DBB_ENABLE;// s1=0,s0=1(Q3)->0(Q2)
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;//DB_ACTV_LOC;//DB_ACTV_HI;//DB_ACTV_LO;//0x00;//DB_ACTV_HIC;// s3=1,s2=0->1, Active Hi complementary
EPwm2Regs.DBFED = 0x05;//INV_DEAD_CYCLE;// FED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBRED = 0x02;//INV_DEAD_CYCLE;// RED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBCTL.bit.OUTSWAP = 0x00;//0x03;
//add soca
EPwm2Regs.ETSEL.bit.SOCAEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCASEL=ET_CTR_PRDZERO;//ET_CTR_PRDZERO;
EPwm2Regs.ETPS.bit.SOCAPRD=ET_1ST;//divide frequency, page69/117.
EPwm2Regs.ETSEL.bit.SOCBEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCBSEL=ET_CTR_PRDZERO;//ET_CTR_ZERO;
EPwm2Regs.ETPS.bit.SOCBPRD=ET_1ST;//divide frequency
EPwm2Regs.ETSEL.bit.INTEN=ET_DISABLE;
EPwm2Regs.ETPS.bit.INTPRD=ET_DISABLE;
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TZ1; // DCAH = TZ1
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;//TZ_DCAH_LOW;//TZ_DCAL_HI_DCAH_LOW;
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; //DCAEVT1 =DCAEVT1(not filtered)
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;//DC_EVT_SYNC;//DC_EVT_ASYNC;//DC_EVT_SYNC;// // Take async path
EPwm2Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm2Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;//TZ_FORCE_LO; // EPWM1B will go low
EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm2Regs.DCACTL.bit.EVT1SYNCE = 1;
1.是有什么寄存器没有配置正确导致的吗，比如shadow register或者AQ之类的导致在写TBPRD的时候会被强制拉低或者拉高？
2.TI有没有相关的变频的例程啊 我找了很久都没找到？
user4669408：
回复 Green Deng:
变频范围在500kHz~1MHz，每次切换的频率不会太大，软件上有限制的
我定频跑500kHz和1MHz都没有问题
此外我发现当我连接XDS100V2 USB 仿真器跑的时候会有一个100kHz的干扰，就是每隔100kHz 时duty就会变大或者变小，其余时刻都正常，当我把程序烧录到Flash 之后跑就没有问题了，请问我这个100kHz是仿真器产生的吗？
