TI中文支持网这里是TI的一个例子，FLL默认是是使用XT1CLK作为FLL的参考时钟FLLREFCLK,然后MCLK使用DCOCLKDIV作为时钟源，但是例子里面使用
问： __bis_SR_register(SCG0); 关闭了FLL，之后MCKL用什么做时钟源呢？
#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
P1DIR |= BIT0; // P1.0 output
P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation
UCSCTL2 = FLLD_1 + 249; // Set DCO Multiplier for 8MHz
// (N + 1) * FLLRef = Fdco
// (249 + 1) * 32768 = 8MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
while(1)
{
P1OUT ^= BIT0; // Toggle P1.0
__delay_cycles(600000); // Delay
}
}
Leon Yan：
你好：
关闭了FLL，DCO依然在工作，仍然可以成为MCLK的时钟源。
而且也可以用REFO和VLO。
谢谢。
Shi JianHua：
回复 Leon Yan:
单片机必须保存一个时钟才行呀
