TI中文支持网Part Number:LMX2487
After the PLL is initialized, R5 and R0 are alternately configured at a frequency of 200Hz to implement 2FSK modulation of the frequency. It is found that the PLL may occasionally malfunction, resulting in failure to lock. Is the PLL's failure to lock related to the alternate configuration of R5 and R0?
Lydia：
您好，
已经收到了您的案例，调查需要些时间，感谢您的耐心等待。
,
Links：
What is your lock time? If you switch the frequency at a rate of 1Hz, will you consistently get it lock?
