TI中文支持网Part Number:TIDA-01022Other Parts Discussed in Thread: ADC12DJ3200
Dome Board gerber with TI 《JESD204B Physical Layer》 unmatched. 
How should I proceed with my design:
1. JESD204B signal, should one choose the inner layer or the surface layer?
2. Do I still need to do the packaging and sealing treatment?
Vivian Gao：
Which document does your screenshot come from? Could you please send the link？Is your question mainly related to TIDA-01022 or ADC12DJ3200AAVR? Because they belong to different sub forums
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chaoqiang chen：
This is the link to the document JESD204B Physical Layer (PHY) https://www.ti.com/lit/ml/slap162/slap162.pdf We are currently using ADC12DJ3200 for the design, so there are some doubts regarding the layout here.
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Vivian Gao：
Ok，please wait for our reply
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Vivian Gao：
JESD Serdes routing does not need to be matched in length, only the P/N inter-pair needs to be, the internal FPGA elastic buffer will take care of the lane delay/mismatches.
I would download and study the layout on our ADC12DJ3100EVM. This will give you good guidance on how to route these serdes lanes and which layers to use.
Typically we route these on the top and/or bottom.
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chaoqiang chen：
OK, thanks! Looking forward to your reply.
