TI中文支持网Part Number:TMS320F280021-Q1Other Parts Discussed in Thread:TMS320F280021
问题：用TMS320F280021做LLC充电过程，ePWM3和ePwm4为驱动H桥LLC，PWM工作频率为80K~150K，为软件设置的上下限值，谐振工作频率为90KHZ。当LLC工作过程进行调节频率从85K往下调节，接近80K时，偶尔有几率有发生半桥上下MOS管驱动同高现象，非百分百，MOS管直通短路，管子烧坏。请问各位大神帮忙审核下配置是否有问题？感谢！
波形如下：
短路前一时刻的驱动波形和频率：
以下为PWM配置代码：
void UserSetEPWM()
{EALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;EDIS;EALLOW;GpioCtrlRegs.GPHAMSEL.bit.GPIO242 = 0;GpioCtrlRegs.GPHQSEL2.bit.GPIO242 = 3;InputXbarRegs.INPUT1SELECT = 242;GpioCtrlRegs.GPHLOCK.bit.GPIO242 = 1;GpioCtrlRegs.GPHCR.bit.GPIO242 = 1;InputXbarRegs.INPUTSELECTLOCK.bit.INPUT1SELECT = 1;EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;EPwm2Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;EPwm3Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;EPwm4Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;EPwm1Regs.TZSEL.bit.OSHT5 = TZ_ENABLE;EPwm2Regs.TZSEL.bit.OSHT5 = TZ_ENABLE;EPwm3Regs.TZSEL.bit.OSHT5 = TZ_ENABLE;EPwm4Regs.TZSEL.bit.OSHT5 = TZ_ENABLE;EPwm1Regs.TZSEL.bit.OSHT6 = TZ_ENABLE;EPwm2Regs.TZSEL.bit.OSHT6 = TZ_ENABLE;EPwm3Regs.TZSEL.bit.OSHT6 = TZ_ENABLE;EPwm4Regs.TZSEL.bit.OSHT6 = TZ_ENABLE;EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO;EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm1Regs.TZFRC.bit.OST = 1;EPwm2Regs.TZFRC.bit.OST = 1;EPwm3Regs.TZFRC.bit.OST = 1;EPwm4Regs.TZFRC.bit.OST = 1;EPwm1Regs.GLDCFG.all = 0x07FF;EPwm1Regs.GLDCTL.bit.GLDMODE = 6;EPwm1Regs.GLDCTL.bit.OSHTMODE = 1;EPwm1Regs.GLDCTL.bit.GLD = 1;EPwm1Regs.EPWMXLINK.bit.GLDCTL2LINK = 0;EPwm2Regs.GLDCFG.all = 0x07FF;EPwm2Regs.GLDCTL.bit.GLDMODE = 6;EPwm2Regs.GLDCTL.bit.OSHTMODE = 1;EPwm2Regs.GLDCTL.bit.GLD = 1;EPwm2Regs.EPWMXLINK.bit.GLDCTL2LINK = 0;EPwm3Regs.GLDCFG.all = 0x07FF;EPwm3Regs.GLDCTL.bit.GLDMODE = 6;EPwm3Regs.GLDCTL.bit.OSHTMODE = 1;EPwm3Regs.GLDCTL.bit.GLD = 1;EPwm3Regs.EPWMXLINK.bit.GLDCTL2LINK = 0;EPwm4Regs.GLDCFG.all = 0x07FF;EPwm4Regs.GLDCTL.bit.GLDMODE = 6;EPwm4Regs.GLDCTL.bit.OSHTMODE = 1;EPwm4Regs.GLDCTL.bit.GLD = 1;EPwm4Regs.EPWMXLINK.bit.GLDCTL2LINK = 0;EDIS;EPwm1Regs.TBPRD = EPWMPeriod;EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT /(HSPCLKDIV ×CLKDIV)EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;//使能同步EPwm1Regs.TBPHS.bit.TBPHS = 0;EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count updownEPwm1Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_DISABLE_ALL;EPwm1Regs.EPWMSYNCOUTEN.bit.ZEROEN = SYNC_OUT_SRC_ENABLE;EPwm2Regs.TBPRD = EPWMPeriod;EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT /(HSPCLKDIV ×CLKDIV)EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;EPwm2Regs.TBPHS.bit.TBPHS = 2;EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count updownEPwm2Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_SYNCOUT_EPWM1;EPwm3Regs.TBPRD = EPWMPeriod;EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT /(HSPCLKDIV ×CLKDIV)EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;EPwm3Regs.TBPHS.bit.TBPHS = 3;//补偿10ns数字隔离器延迟EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count updownEPwm3Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_SYNCOUT_EPWM1;EPwm4Regs.TBPRD = EPWMPeriod;EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT /(HSPCLKDIV ×CLKDIV)EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;EPwm4Regs.TBCTL.bit.PHSDIR = TB_UP;EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;EPwm4Regs.TBPHS.bit.TBPHS = 3;//补偿10ns数字隔离器延迟EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count updownEPwm4Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_SYNCOUT_EPWM1;EPwm5Regs.TBPRD = 1000;EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT /(HSPCLKDIV ×CLKDIV)EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;EPwm5Regs.TBCTL.bit.PHSDIR = TB_UP;EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE;
//EPwm5Regs.TBPHS.bit.TBPHS = 2;//补偿10ns数字隔离器延迟EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Count updownEPwm5Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_DISABLE_ALL;//计数比较模块设定EPwm1Regs.TBCTR = 0; //计数初值为0EPwm1Regs.CMPA.bit.CMPA = EPWMPeriod_DIV2 - LeastTime_LLC;EPwm1Regs.CMPB.bit.CMPB = EPWMPeriod_DIV2 + LeastTime_LLC;EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm2Regs.TBCTR = 0; //计数初值为0EPwm2Regs.CMPA.bit.CMPA = EPWMPeriod_DIV2 - LeastTime_LLC;EPwm2Regs.CMPB.bit.CMPB = EPWMPeriod_DIV2 + LeastTime_LLC;EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm3Regs.TBCTR = 0; //计数初值为0EPwm3Regs.CMPA.bit.CMPA = EPWMPeriod_DIV2 - LeastTime_LLC;EPwm3Regs.CMPB.bit.CMPB = EPWMPeriod_DIV2 + LeastTime_LLC;EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm4Regs.TBCTR = 0; //计数初值为0EPwm4Regs.CMPA.bit.CMPA = EPWMPeriod_DIV2 - LeastTime_LLC;EPwm4Regs.CMPB.bit.CMPB = EPWMPeriod_DIV2 + LeastTime_LLC;EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm5Regs.TBCTR = 0; //计数初值为0
//EPwm5Regs.CMPA.bit.CMPA = 0;
//EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
//EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;// AQ模块设定EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;EPwm1Regs.AQCTLA.bit.CBU = AQ_CLEAR;EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;EPwm2Regs.AQCTLB.bit.CAU = AQ_SET;EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;EPwm2Regs.AQCTLA.bit.CBD = AQ_SET;EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR;EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR;EPwm3Regs.AQCTLB.bit.CBD = AQ_SET;EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR;EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR;EPwm4Regs.AQCTLB.bit.CAU = AQ_SET;EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;EPwm4Regs.AQCTLA.bit.CBD = AQ_SET;EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;EPwm4Regs.AQCTLA.bit.ZRO = AQ_CLEAR;EPwm4Regs.AQCTLB.bit.ZRO = AQ_CLEAR;//DB死区模块设定EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;EPwm1Regs.GLDCTL2.bit.GFRCLD = 1;EPwm5Regs.ETSEL.bit.SOCAEN = 1;// 1 Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse, Enable EPWMxSOCB pulse.EPwm5Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;//PRD 触发ADC_BEPwm5Regs.ETPS.bit.SOCAPRD = ET_1ST;
//EPwm1Regs.ETSEL.bit.INTEN = 1;// 1 Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse, Enable EPWMxSOCB pulse.
//EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;//PRD 触发ADC_B
//EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;EALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;EDIS;
}
以下为PWM转载代码：
void loadpwm()
{F_SW = CC_PID.PIDU;//PI计算值F_SW = __fmin(150,F_SW);F_SW = __fmax(80,F_SW);EPWMPeriod = 50000 / F_SW;EPWMPeriod_DIV2 = EPWMPeriod / 2;LLC_Hduty_EPWM = LLC_duty * EPWMPeriod_DIV2;if( LLC_Hduty_EPWM > EPWMPeriod_DIV2 - 25 ){LLC_Hduty_EPWM = EPWMPeriod_DIV2 - 25;}EPWMPeriod = EPWM_Cal_SW / F_SW;EPWMPeriod_DIV2 = EPWMPeriod / 2;EPWMPeriod = EPWMPeriod_DIV2 * 2;F_Int = 50;T_Ctrl = 0.001f/F_Int;EPwm3Regs.TBPRD = EPWMPeriod;//Period of TB = 10kHzEPwm4Regs.TBPRD = EPWMPeriod;//Period of TB = 10kHzEPwm3Regs.CMPA.bit.CMPA = EPWMPeriod_DIV2 - LLC_Hduty_EPWM;EPwm3Regs.CMPB.bit.CMPB = EPWMPeriod_DIV2 + LLC_Hduty_EPWM;EPwm4Regs.CMPA.bit.CMPA = EPWMPeriod_DIV2 - LLC_Hduty_EPWM;EPwm4Regs.CMPB.bit.CMPB = EPWMPeriod_DIV2 + LLC_Hduty_EPWM;EPwm1Regs.GLDCTL2.bit.OSHTLD = 1;
}
user5229665：
按理说配置了死区不应该出现上下桥直通呀，检查一下DBCTL.POLSEL的配置呢？
,
qin jfefy：
POLSEL寄存器没有配置，默认00模式。按理应该也没事。所有也很奇怪现象，理论有死区不可能直通，但是我的产品可以正常工作，只在LLC控制的充电电流有抖动，LLC频率往下限频率调节过程就有一定概率发生。
,
Yale Li：
1. 波形是从哪个管脚抓取的？F280021的PWM输出管脚？还是MOS管的预驱？
qin jfefy 说：偶尔有几率有发生半桥上下MOS管驱动同高现象，
2. 这个是说一个器件上有很小的机率碰到这个问题？还是许多产品中有一小部分有问题？
qin jfefy 说：
波形如下：
3. 出现短路的这个周期，周期值和正常相比有变化吗？
,
Yale Li：
楼主的死区不是通过DB模块做出来的，DB模块相当于是直接被bypass掉的。
,
Yale Li：
Yale Li 说：1. 波形是从哪个管脚抓取的？F280021的PWM输出管脚？还是MOS管的预驱？
之所以问这个问题是因为我们现在没有办法判断问题是跟随C2000的还是跟随MOS管的。
从第一二张波形来看，发生问题时，上下管直通造成短路，波形剧烈跳变，之后MOS管烧毁断路。
一种可能是C2000的动作出了问题；
由于问题出现在高频变为低频时，也有可能是因为MOS管导通时间增加，导致关断失败。
现在应该先判断一下问题是跟随谁。
如果设计中，在C2000与MOS之间的PWM信号有隔离或者缓冲，也就是说信号是从C2000单向流向MOS的，这样MOS的状态就不会影响从C2000发出的原始的PWM波形，我们就能做出进一步的判断。
,
qin jfefy：
1. 波形是从哪个管脚抓取的？F280021的PWM输出管脚？还是MOS管的预驱？
答：波形是从MCU的PWM输出IO口抓取的，上图电平均为3.3V。如下图，U10左边为MCU IO，右边接MOS管G极：
2. 这个是说一个器件上有很小的机率碰到这个问题？还是许多产品中有一小部分有问题？
答：每个器件都是概率发生，只是发生的条件为充电，起机过程LLC输出拉载的几秒钟，LLC输入电压有下降，然后LLC进行调频，频率接近下限频率80K左右，就有可能发生同桥直通短路。但不是每次都发生，多次测试才会偶尔出现。
如下图为短路瞬间的波形，PI参数没怎么调好，发生了输出震荡：蓝色为LLC输入电压，黄色为LLC谐振电感电流、绿色为LLC输出电流。
3. 出现短路的这个周期，周期值和正常相比有变化吗？
答：1楼中图3为短路前一时刻的频率为85K，短路瞬间上管（黄色波形）的频率也是85K左右，变化不大，下管（绿色波形）就持续高电平拉不下来，造成了短路。
,
qin jfefy：
一种可能是C2000的动作出了问题；
由于问题出现在高频变为低频时，也有可能是因为MOS管导通时间增加，导致关断失败。
现在应该先判断一下问题是跟随谁。
如果设计中，在C2000与MOS之间的PWM信号有隔离或者缓冲，也就是说信号是从C2000单向流向MOS的，这样MOS的状态就不会影响从C2000发出的原始的PWM波形，我们就能做出进一步的判断。
我们设计的LLC从MCU出来的信号经过了隔离IC后，再到MOS驱动IC的，理论MOS管的状态不会影响到C2000发出来的原始波形。理论频率从高到低调节，PWM的周期改变也是在下一个周期开始从影子寄存器取值，不至于一个上管的脉宽和下管的脉宽不一样吧。
,
Yale Li：
我已经向相关工程师寻求帮助：
https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1296573/tms320f280021-q1-epwm-output-not-clear-as-expect-lead-llc-circuit-h-bridge-mos-short
,
Yale Li：
我们注意到有相同的问题已经在E2E上发布：
https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1295694/tms320f280021-q1-epwm-for-llc-control-process-pwm-outputs-are-both-high-level-issue
我们的工程师会在该帖中继续支持
,
qin jfefy：
好的，谢谢！
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Yale Li：
客气了~
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qin jfefy：
我们今天发现通过模拟LLC频率跳变，在demo板上运行，也会发送同桥直通现象，我在那个贴上把我的发现和疑问添加进去了。
,
Yale Li：
好的
,
qin jfefy：
我有一个疑问，我的ePWM配置开了全局装载
EPwm3Regs.GLDCFG.all = 0x07FF;
EPwm4Regs.GLDCFG.all = 0x07FF;
AQ模块的如下还需要单独配置吗？
EPwm3Regs.AQCTL.bit.SHDWAQAMODE = AQ_CLEAR; EPwm3Regs.AQCTL.bit.SHDWAQBMODE = AQ_CLEAR;
EPwm4Regs.AQCTL.bit.SHDWAQAMODE = AQ_CLEAR;EPwm4Regs.AQCTL.bit.SHDWAQBMODE = AQ_CLEAR;
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Yale Li：
不需要，全局装载会取代影子寄存器
