TI中文支持网Part Number:SN65DP159Other Parts Discussed in Thread:TDP142, SN65DP141
目前我们有在使用DP159 retimer这个芯片，这个芯片主要用于DP信号的加强，我们在使用这个芯片时碰到以下几个问题：
- DP159完成PLL Locked的时间一般是多久，以及最大的等待时间建议是多少，没有完成PLL Locked是否需要重新完整配置一遍DP159？
- 偶发开机上电，显示屏No Signal，抓取MCU配置DP159的IIC数据，发现读取DP159的LOCK_COMPLETE status，结果是0xE3，是Locked状态，但没有显示，显示屏一直发送HPD 的unplug信号，MCU反复配置仍然没法显示，这个算是DP159的异常状态吗？
- Xilinx有一份用于配置DP159的C文件，c、xdprss_dp159.h见附件，里面的配置流程与规格书推荐的基本一致，但是不同阶段部分配置寄存器种类有差异，需要现场支持解释一下对应的功能和影响，特别是针对DP159的配置寄存器的含义；
- 规格书推荐的DP159寄存器配置，只有一个回读的寄存器LOCK_COMPLETE status进行状态确认，其它的全为写入操作，如何确保寄存器配置成功，LOCK_COMPLETE status置位即可认为配置成功？
- datarate、lane count、sink removal or DP Source no longer detected，推荐配置部分寄存器即可，如果重新完整配置一遍（相当于上电初始化），有没有问题，对于DP159的此次上电的正常工作有无负面影响？
以下是我们固件的配置流程：
David (ASIC) Liu：
Hi,
The DP159 as a DP re-timer is intended for the sink side with Xilinx FPGA, it was not intended to be used on the source side since DP159 TX output is not compliant to the DP spec.
For source side, please use TDP142 or SN65DP141.
Thanks
David
,
Eric Liu(SZ-FAE)：
Hi David ，
Thx for your reply，
can you show me the answer for the following questions？
1、What is the typical time for DP159 to complete the PLL locked and what is the maximum recommended wait time, do you need to re-configure the DP159 once without the PLL locked?
2、Power up occasionally, display No Signal, grab MCU configuration DP159 IIC data, find lock_complete status reading DP159, The result is 0xE3, locked state, but not shown, the display always sends the unplug signal of HPD. The MCU is still not able to be displayed over and over again, is this a DP159 abnormal state?
3、Xilinx has a C file for configuring DP159, xdprss_dp159.c, xdprss_dp159.h is attached. The configuration flow is basically as recommended in the specification. However, some of the configuration register types vary from stage to stage and require field support to explain the functionality and impact, especially the meaning of the configuration register for DP159.
4、The DP159 register configuration recommended by the specification has only one read-back register lock_complete status for status confirmation, all other writes, how to ensure successful register configuration. Can lock_complete status be set to consider provisioning successful?
5.datarate, lane count, sink removal or DP Source no longer detected. Recommended to configure some of the registers. If the registers are completely reconfigured once (equivalent to power-up initialization), there is a problem. Is there any negative impact to the proper operation of this power up of DP159?
