AM2634: [Cortex_R5_0] ASSERT: 0.3s: soc/am263x/soc_rcm.c:SOC_rcmGetCoreFout:1521: FOut != 0 failed !!!

Part Number:AM2634

can you please write in english what is the resolution. I have sdk_am263x_08_05_00_24. And all the time have the [Cortex_R5_0] ASSERT: 0.3s: soc/am263x/soc_rcm.c:SOC_rcmGetCoreFout:1521: FOut != 0 failed !!!

Nancy Wang:

Can you describe in detail the problem you are experiencing?

The last relpy in the original post:

Using debug mode and you can connect. And as long as the sbl is flashed, we can also boot from other modes. If sbl is erased, it can only enter the debug mode to boot.


Andrei Zinenko:

AM263x-cc evaluation board and examples from SDK 08-05-00-24.

Without any changes in board or examples all the time get this error:

[Cortex_R5_0] ASSERT: 0.3s: soc/am263x/soc_rcm.c:SOC_rcmGetCoreFout:1521: FOut != 0 failed !!!

1. I tried the several projects:

     – adc_soc_continuous_am263x-cc_r5fss0-0_nortos_ti-arm-clang

    – gpio_multi_led_blink_am263x-cc_r5fss0-0_nortos_ti-arm-clang

2. I use QSPI BOOT MODE in AM263X-CC evaluation board

3. I use the project as is and I can conclude it uses the GEL scripts from this:


Cortex_R5_0: GEL Output: Loading Gel Files on R5F0Cortex_R5_0: GEL Output: Gel files loading on R5F0 CompleteCortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263x Initialization Scripts Launched.Please Wait…

Cortex_R5_0: GEL Output: AM263x_Cryst_Clock_Loss_Status() LaunchedCortex_R5_0: GEL Output: Crystal Clock presentCortex_R5_0: GEL Output: AM263x_SOP_Mode() LaunchedCortex_R5_0: GEL Output: SOP MODE = 0x00000004Cortex_R5_0: GEL Output:QSPI – 4S Fallback UART boot modeCortex_R5_0: GEL Output: AM263x_Read_Device_Type() LaunchedCortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AACortex_R5_0: GEL Output: AM263x_Check_supported_mode() LaunchedCortex_R5_0: GEL Output:efuse1=0x01000000Cortex_R5_0: GEL Output:The Device supports both LockStep & Dual Core modeCortex_R5_0: GEL Output:mode = 0Cortex_R5_0: GEL Output: MSS_CTRL Control Registers UnlockedCortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers UnlockedCortex_R5_0: GEL Output: MSS_RCM Control Registers UnlockedCortex_R5_0: GEL Output: MSS_IOMUX Control Registers UnlockedCortex_R5_0: GEL Output: TOP_CTRL Control Registers UnlockedCortex_R5_0: GEL Output:

***R5FSS0 Reset for Lockstep ***Cortex_R5_0: GEL Output:

*** R5FSS1 Reset for Lockstep ***Cortex_R5_0: GEL Output: R5F ROM EclipseCortex_R5_0: GEL Output: R5FSS0_0 ReleasedCortex_R5_0: GEL Output: R5FSS0_1 ReleasedCortex_R5_0: GEL Output: R5FSS1_0 ReleasedCortex_R5_0: GEL Output: R5FSS1_1 ReleasedCortex_R5_0: GEL Output:

All R5F Cores Released for program loadCortex_R5_0: GEL Output: L2 Mem Init CompleteCortex_R5_0: GEL Output: MailBox Mem Init CompleteCortex_R5_0: GEL Output: *********** R5FSS0/1 Lockstep mode Configured********Cortex_R5_0: GEL Output: PER PLL Configuration CompleteCortex_R5_0: GEL Output: SYS_CLK DIVBY2Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKsCortex_R5_0: GEL Output:CLK Programmed R5F=400MHz and SYS_CLK=200MHzCortex_R5_0: GEL Output:

*** Enabling Peripheral Clocks ***Cortex_R5_0: GEL Output: Enabling RTI[0:3] ClocksCortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] ClocksCortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] ClocksCortex_R5_0: GEL Output: Enabling QSPI ClocksCortex_R5_0: GEL Output: Enabling I2C ClocksCortex_R5_0: GEL Output: Enabling TRACE ClocksCortex_R5_0: GEL Output: Enabling MCAN[0:3] ClocksCortex_R5_0: GEL Output: Enabling GPMC ClocksCortex_R5_0: GEL Output: Enabling ELM ClocksCortex_R5_0: GEL Output: Enabling MMCSD ClocksCortex_R5_0: GEL Output: Enabling MCSPI[0:4] ClocksCortex_R5_0: GEL Output: Enabling CONTROLSS ClocksCortex_R5_0: GEL Output: Enabling CPTS ClocksCortex_R5_0: GEL Output: Enabling RGMI[5,50,250] ClocksCortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K ClocksCortex_R5_0: GEL Output: Enabling XTAL_MMC_32K ClocksCortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL.


Andrei Zinenko:

More information.

That is what I found after some debugging

in file soc_rom.c in functionn SOC_rcmGetCoreFout()

When it NOT works:

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65547

causing N = 11

ptrTopRCMRegs->PLL_CORE_MN2DIV = 65920

causing M = 384

Then with this parameters it cannot match any entry in table 

const SOC_RcmADPLLJConfig_t gADPLLJConfigTbl[] ={ /* CORE_2000_25MHz */ { .Finp = 25U, .N = 9U, .Fout = 2000U, .M2 = 1U, .M = 800U, .FracM = 0U, }, /* PER_1920_25MHz */ { .Finp = 25U, .N = 9U, .Fout = 1920U, .M2 = 1U, .M = 768U, .FracM = 0U, },};

causing function SOC_rcmADPLLJGetFOut() return FOut = 0

From time to time it do works. Then:

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65545

causing N = 9

ptrTopRCMRegs->PLL_CORE_MN2DIV = 768

causing M = 768

causing function SOC_rcmADPLLJGetFOut() return Fout = 1920*1000 *1000

May be this can give you some direction



Andrei Zinenko:

Do you have any idea why 

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65547


ptrTopRCMRegs->PLL_CORE_MN2DIV = 65920




Nancy Wang:


I am not familiar with AM2634, please post on e2e, there will be relevant experts to support you.



Andrei Zinenko:

NO BOOT mode resolved this issue.


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