TI中文支持网Part Number:MSP430FR5969
- Everyone, i wanna ask some questions. If the cpu works in lpm( low-power-mode), and i wanna use adc-12 to keep measuring a successive signal then store it into a flash outside the mpu. Can i just use DMA to achieve this goal instead of awaking CPU?
- helppppp! THANKS
Cherry Zhou：
Hi, we have received your questions and feedback to the engineer, if there is any updates I will reach you asap!
Thanks!
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Cherry Zhou：
Runhua Wang 说：Everyone, i wanna ask some questions. If the cpu works in lpm( low-power-mode), and i wanna use adc-12 to keep measuring a successive signal then store it into a flash outside the mpu.
The DMA can be used with the ADC, operating in the background with the CPU in LPM. here's an example for the F5 series, which has a similar ADC and DMA:
https://www.ti2k.com/wp-content/uploads/ti2k/DeyiSupport_MSP430_node
For the ADC with DMA in LPM, here's a project that created before with FR5994 that you can take as a reference:
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/166/adc_5F00_dma_5F00_with_5F00_lea_5F00_4k.zip
Runhua Wang 说：Can i just use DMA to achieve this goal instead of awaking CPU?
The FR5994 doesn't have an external bus (EMIF), so writing to an external flash would presumably use a serial port — probably SPI. This can also be done with the DMA, but coordination with the ADC DMA would require some CPU intervention. (I don't know of a TI Example.)
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Runhua Wang：
Thank you so so much! It helps a lot.
And i has another question that can i read and write at the FRAM in MPU at the same time?
Because i wanna keep the ADC measuring to FRAM and at the same time transmit the data in FRAM to the external flash.
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Cherry Zhou：
Hi noted, I have updated your question to the engineer, if there is response I will follow up to you asap.
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Cherry Zhou：
An address (range) can be configured for both read and write in the Memory Protection Unit (MPU).
DMA memory operations don't occur simultaneously, nor do CPU memory operations — DMA operations happen in priority order, and the CPU is stalled during DMA.
