TI中文支持网Part Number:MSP430FR5969
Hi,
As shown in document, the MSP430FR5969 has error-correcting code FRAM. We implemented the ECC code with the method shown in the "MSP430 Assembly Language Tools".
After a data error was injected, we downloaded the code to the MSP430 board. The data error was not corrected after power on.
How can we implement the ECC function with CCS? Could you please provide more details and give us some document on it? Thanks a lot!
Cherry Zhou：
Hi we have got your issue and escalated to e2e. Please expect the response! Thanks.
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Cherry Zhou：
Hi,
1. Do you configure the ECC refer to this:
2. To check whether the ECC works, you can check the register GCCTL0 in debug mode.
3. Can you give more explain about "After a data error was injected, we downloaded the code to the MSP430 board. The data error was not corrected after power on.". It seems that you put a wrong data into the code, and download the code into FRAM. Then hope ECC to correct it. Is it right?
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Jack John：
Hi,
1, We configure the ECC with linker as below
2, The linker output was shown belown
3, We download the code with error bit in debug mode,the register GCCTL0 remained zero. The ECC interupt was not triggered.
Were the procedures shown above right?
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Cherry Zhou：
It appears that some flash parts have ECC (we have never seen one). Also, it appears that the ECC information is either calculated by the linker, or accessible somehow on the part. That is not the case with FRAM. Each write of data to FRAM causes the ECC information to be computed on the fly. Each read too since FRAM has a destructive read.
The FRAM ECC hardware does signal when it runs into errors and you can check that.
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Jack John：
Is the FRAM word size 80 bits (64 bits of data, 16 bits of ECC)?
Is the ECC 8 bits or 16 bits?
If we want to tigger one bit ECC error, should we try to read 64 bits?
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Jack John：
Could you please us some example project codes with ECC function?
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Annie Liu：
The internals of the FRAM ECC are a black box known only to TI. I seem to recall some discussion in another thread, but it doesn't really matter. It will correct all single bit errors and detect most others.
You can't trigger an ECC error, only field an interrupt (if enabled) when one occurs. Any read that results in a cache miss requiring an FRAM read has a tiny chance of resulting in an ECC error. Very tiny.
slaa526 says: "The tests indicate that the SER for FRAM is orders of magnitude lower than SRAM."
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Cherry Zhou：
You could take it to a cyclotron, bombard it with ions and try to induce an SEU.
