TI中文支持网如题，在用28035做BLDC六步换向法控制时，设置了上下桥互补交替调制。
但是每次换向时第一个脉冲不受控，与自己设置的比较值相差较大，导致电流过大。请帮忙看看能如何解决？谢谢大佬们
Green Deng：
你好，由于你提供的信息相对较少，不太确定问题所在，可以先参考一下这个帖子的内容，与你问题相似，只是出问题的原因不同：
e2echina.ti.com/…/197221
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user5159416：
您好，看了那篇帖子，将装载模式设置为立即装载。但是还是没有效果。
我做的主要是方波的六步换向控制，每换一相，需要EPWM由调制转为常开或常闭。但是每次调制的第一个脉宽宽度与我设置的占空比不对。
我在想是否是在换向时与EPWM的计数值不一致导致的原因，在换向前有将计数值清零 Epwm1Regs.TBCTR = 0，但发现Epwm1Regs.TBCTR 溢出（大于当前周期值TBPRD）。请问该如何设置呢？
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user5159416：
附上EPWM配置和波形图
EPWM配置：
\ EALLOW; \ SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; \ EDIS; \ \ /* Init Timer-Base Period Register for EPWM1-EPWM3*/ \ EPwm1Regs.TBPRD = v.PWMprd; \ EPwm2Regs.TBPRD = v.PWMprd; \ EPwm3Regs.TBPRD = v.PWMprd; \ \ /* Init Timer-Base Counter Register for EPWM1-EPWM3*/ \ EPwm1Regs.TBCTR = 0x0000; \ EPwm2Regs.TBCTR = 0x0000; \ EPwm3Regs.TBCTR = 0x0000; \ \ /* Init Compare Register for EPWM1-EPWM3 to 50% duty cycle */ \ EPwm1Regs.CMPA.half.CMPA = v.PWMprd/2; \ EPwm2Regs.CMPA.half.CMPA = v.PWMprd/2; \ EPwm3Regs.CMPA.half.CMPA = v.PWMprd/2; \ \ /* Init Timer-Base Phase Register for EPWM1-EPWM3*/ \ EPwm1Regs.TBPHS.half.TBPHS = 0; \ EPwm2Regs.TBPHS.half.TBPHS = 0; \ EPwm3Regs.TBPHS.half.TBPHS = 0; \ \ /* Init Timer-Base Control Register for EPWM1-EPWM3*/ \ EPwm1Regs.TBCTL.all = PWM_CNTL_INIT_STATE; \ EPwm2Regs.TBCTL.all = PWM_CNTL_INIT_STATE; \ EPwm3Regs.TBCTL.all = PWM_CNTL_INIT_STATE; \ \ /* Setup Sync*/ \ EPwm3Regs.TBCTL.bit.SYNCOSEL = 1; \ EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; \ EPwm1Regs.TBCTL.bit.SYNCOSEL = 0; \ \ /* Allow each timer to be sync'ed*/ \ EPwm3Regs.TBCTL.bit.PHSEN = 0; \ EPwm2Regs.TBCTL.bit.PHSEN = 1; \ EPwm1Regs.TBCTL.bit.PHSEN = 1; \ \ /* Set count dir after sync event*/ \ EPwm3Regs.TBCTL.bit.PHSDIR = 0; \ EPwm2Regs.TBCTL.bit.PHSDIR = 1; \ EPwm1Regs.TBCTL.bit.PHSDIR = 1; \ \ /* Init Compare Control Register for EPWM1-EPWM3 */ \ EPwm1Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE; \ EPwm2Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE; \ EPwm3Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE; \ \ /* Init Action Qualifier Output A Register for EPWM1-EPWM3*/ \ EPwm1Regs.AQCTLA.all = PWM_CNTL_AQCTLA_INIT_STATE_4; \ EPwm2Regs.AQCTLA.all = PWM_CNTL_AQCTLA_INIT_STATE_4; \ EPwm3Regs.AQCTLA.all = PWM_CNTL_AQCTLA_INIT_STATE_4; \ \ /* Init Dead-Band Generator Control Register for EPWM1-EPWM3*/ \ EPwm1Regs.DBCTL.all = DBCTL_INIT_STATE; \ EPwm2Regs.DBCTL.all = DBCTL_INIT_STATE; \ EPwm3Regs.DBCTL.all = DBCTL_INIT_STATE; \ \ /* Init Dead-Band Generator for EPWM1-EPWM3*/ \ EPwm1Regs.DBFED = DBCNT_INIT_STATE; \ EPwm1Regs.DBRED = DBCNT_INIT_STATE; \ EPwm2Regs.DBFED = DBCNT_INIT_STATE; \ EPwm2Regs.DBRED = DBCNT_INIT_STATE; \ EPwm3Regs.DBFED = DBCNT_INIT_STATE; \ EPwm3Regs.DBRED = DBCNT_INIT_STATE; \ \ /* Init PWM Chopper Control Register for EPWM1-EPWM3*/ \ EPwm1Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE; \ EPwm2Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE; \ EPwm3Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE; \ \ \
其中
#define PWM_CNTL_INIT_STATE ( FREE_RUN_FLAG + \ PRDLD_SHADOW + \ TIMER_CNT_UPDN + \ HSPCLKDIV_PRESCALE_X_1 + \ CLKDIV_PRESCALE_X_1 + \ PHSDIR_CNT_UP + \ CNTLD_DISABLE )
#define BLDCPWM_CMPCTL_INIT_STATE ( LOADAMODE_ZRO + \ LOADBMODE_ZRO + \ SHDWAMODE_IMMEDIATE + \ SHDWBMODE_IMMEDIATE )
#define PWM_CNTL_AQCTLA_INIT_STATE_4 ( PRD_SET + CAU_CLEAR )
#define DBCTL_INIT_STATE (BP_ENABLE + POLSEL_ACTIVE_HI_CMP)
#define BLDCPWM_PCCTL_INIT_STATE CHPEN_DISABLE
换向部分函数：
#define MOD6CNTDIR_MACRO(v) \ \ if (v.TrigInput > 0) \ { \ if(v.Counter == 5) \ { \ v.Counter = 0; \ data=data+1; \ datasa=1; \ EPwm1Regs.TBCTR = 3000; \ EPwm2Regs.TBCTR = 3000; \ EPwm3Regs.TBCTR = 3000; \ } \ else \ { \ v.Counter++; \ EPwm1Regs.TBCTR = 3000; \ EPwm2Regs.TBCTR = 3000; \ EPwm3Regs.TBCTR = 3000; \ } \ }
有时会出现后面这种叠加，有时是主贴的第一个脉冲宽度不同
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Green Deng：
你好，我把你的问题升级至英文版E2E论坛了，由于后续两天是周末，可能无法及时回复，你可以前往以下链接帖子查看回复：
e2e.ti.com/…/983723
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Green Deng：
你好，有工程师在E2E论坛上回复了，是否有查看？能否对工程师提出的问题给予确认？
