TI中文支持网如标题所示，我在使用ePWM X-BAR将CMPSS的比较输出信号CTRIPH路由为TRIP4输入到DC子模块，程序单核CPU1运行正常，放到CPU2中运行不正常，请问可能使什么原因，两个方案的代码基本相同；
双核PWM程序以及运行成功，使用CPU1运行PWM1~3, CPU2运行PWM4~6，代表PWM其余模块基本配置·正确；但是在CPU2中增加PWM模块DC子模块的代码后，ePWM X-BAR的Trip输入不能触发DC子模块的事件DCEVTA1/DCEVTB1发生；（相同的程序代码单核CPU1运行是可行的）
//—————————————————————————————
// 双核运行代码
//****************CPU1运行代码(ePWM X-BAR与主机选择应用配置相关部分)************************
// Transfer ownership of EPWM1 and ADCA to CPU02
// 将EPWM4~6、ADC_C/D、EQEP2,CMPSS6~8的主机配置为CPU2
DevCfgRegs.CPUSEL0.bit.EPWM4 = 1;
DevCfgRegs.CPUSEL0.bit.EPWM5 = 1;
DevCfgRegs.CPUSEL0.bit.EPWM6 = 1;
DevCfgRegs.CPUSEL2.bit.EQEP2 = 1;
DevCfgRegs.CPUSEL12.bit.CMPSS6 = 1;
DevCfgRegs.CPUSEL12.bit.CMPSS7 = 1;
DevCfgRegs.CPUSEL12.bit.CMPSS8 = 1;
DevCfgRegs.CPUSEL11.bit.ADC_C = 1;
DevCfgRegs.CPUSEL11.bit.ADC_D = 1;
// TRIP5: motor2三相电流采样信号经过比较器后的输出进行或逻辑运算,CMPSS6~8:CTRIPOUTH OR CTRIPOUTL;
/*********************Code for Debug*********************/
// InputXbarRegs.INPUT5SELECT = 19; // Configure GPIO52 as INPUT2 of INPUT X-BAR
// EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX9 = 1; //CMPSS6.CTRIPOUTH_OR_CTRIPOUTL
// EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX9 = 1; //Enable MUX10 to drive the TRIP4;
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX10 = 1; //CMPSS6.CTRIPOUTH_OR_CTRIPOUTL
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX12 = 1; //CMPSS7.CTRIPOUTH_OR_CTRIPOUTL
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX14 = 1; //CMPSS8.CTRIPOUTH_OR_CTRIPOUTL
EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX10 = 1; //Enable MUX10 to drive the TRIP4;
EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX12 = 1; //Enable MUX12 to drive the TRIP4;
EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX14 = 1; //Enable MUX14 to drive the TRIP4;
//****************CPU2运行代码************************
/* DC子模块寄存器配置，配合EPWM XBAR与CMPSS模块实现硬件过流保护功能，可选功能*/
// 若是CMPSS比较器输入信号噪声较大，还可以使能event filter滤波功能，与GPIO的采样窗限定差不多，这里暂时不配置；
/* DCACTL/DCBCTL控制寄存器默认选择DCAEVT1/2,DCBEVT1/2作为输入, 将滤波后的信号DCEVTFILT旁路*/
#ifdef EPWM_XBAR_DC
// 因为DCAEVT1,DCBEVT1才可用作OST触发TZ，DCAEVT2,DCBEVT2仅可用作CSC触发TZ，因此要将1个TRIP触发输出到两个事件force信号;
// 在Device_Init.c文件中配置了EPWM XBAR功能，将多个相电流采样ADC引脚复用为CMPSS输入引脚，单电机三个输出经过或运算后综合到TRIP4(motor1)与TRIP5(motor2)引脚;
// motor2对应TRIP5输入，对应EPWM4~6寄存器配置;
EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 4; //4,TRIP5
EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 4; //4,TRIP5
EPwm4Regs.TZDCSEL.bit.DCAEVT1 = 2; //010:DCAH = high,DCAL = don't care, DC A Event 1 Selection
EPwm4Regs.TZDCSEL.bit.DCBEVT1 = 2; //010:DCBH = high,DCBL = don't care, DC B Event 1 Selection
EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; //1, Source is passed through asynchronously
EPwm5Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 4; //4,TRIP5
EPwm5Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 4; //4,TRIP5
EPwm5Regs.TZDCSEL.bit.DCAEVT1 = 2; //010:DCAH = high,DCAL = don't care, DC A Event 1 Selection
EPwm5Regs.TZDCSEL.bit.DCBEVT1 = 2; //010:DCBH = high,DCBL = don't care, DC B Event 1 Selection
EPwm5Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; //1, Source is passed through asynchronously
EPwm6Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 4; //4,TRIP5
EPwm6Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 4; //4,TRIP5
EPwm6Regs.TZDCSEL.bit.DCAEVT1 = 2; //010:DCAH = high,DCAL = don't care, DC A Event 1 Selection
EPwm6Regs.TZDCSEL.bit.DCBEVT1 = 2; //010:DCBH = high,DCBL = don't care, DC B Event 1 Selection
EPwm6Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; //1, Source is passed through asynchronously
#endif
#ifdef EPWM_XBAR_DC //(其实该部分已经在EPWM_INit.c文件的DC子模块寄存器配置中配置过了)
//若还要使能EPWM的XBAR与DC模块配合输出的硬件TZ保护，使用以下配置
#define TZSEL_INIT_STATE (ENABLE_TZ2_OST+ENABLE_DCAEVT1_OST+ENABLE_DCBEVT1_OST)
#else
#define TZSEL_INIT_STATE (ENABLE_TZ2_OST)
#endif
/*—————————————————————————-
Initialization constant for the F2833X Trip Zone Control Register
—————————————————————————-*/
#ifdef EPWM_XBAR_DC
//若还要使能EPWM的XBAR与DC模块配合输出的硬件TZ保护，使用以下配置
#define TZCTL_INIT_STATE (TZA_FORCE_LO+TZB_FORCE_LO+DCAEVT1_FORCE_LO+DCBEVT1_FORCE_LO)
#else
#define TZCTL_INIT_STATE ( TZA_FORCE_LO + TZB_FORCE_LO )
#endif
//——————————————————————————
/* Init Trip Zone Select Register*/
/***这个地方是使能 Enable TZ1 TZ2 as a one-shot trip source for this ePWM module*/
/* 当外部TZ被触发时，TZCTL将把相关引脚拉低 */
// 利用INPUT XBAR功能将IPM Error1引脚连接到内部TZ1引脚上，IPM Error2引脚连接到内部TZ2引脚上；
// IPM Error低电平有效，TZ信号也是低电平触发；即使有IPM_Error引脚悬空未接，使能GPIO上拉电阻默认为高电平，不会触发TZ；
// 通过TZCLR[OST]位清除TZFLG[OST]标志位，已经宏定义为Enable_PWMx_TZ
// 此外，条件编译可选使用EPWM XBAR与DC子模块做硬件电流保护方案；
EPwm4Regs.TZSEL.all = TZSEL_INIT_STATE;
EPwm5Regs.TZSEL.all = TZSEL_INIT_STATE;
EPwm6Regs.TZSEL.all = TZSEL_INIT_STATE;
EPwm4Regs.TZCTL.all = TZCTL_INIT_STATE; //TZA_FORCE_LO + TZB_FORCE_LO
EPwm5Regs.TZCTL.all = TZCTL_INIT_STATE; //TZA_FORCE_LO + TZB_FORCE_LO
EPwm6Regs.TZCTL.all = TZCTL_INIT_STATE; //TZA_FORCE_LO + TZB_FORCE_LO
//*****************************************
想了半天没想明白原因，求大佬解答，或者提供一个思路，为什么相同代码，单核可以运行，双核运行失败？
Susan Yang：
您将能够分别使用由CPU1和CPU2控制的2个不同的IO / XBAR输入吗？现在是CPU2不成功？
CPU1 CPU2 都可以配置为所有PWM的trip 源，即任一CPU都可以通过控制相应CPU拥有的IO使所有PWM trip 。
关于CPU2使用，您需要
1 初始化TZ
2 CPU2向GPDAT寄存器写入1，这将在切换CPU所有权时将IO的状态保持为高
3 将GPIO的控制权传递给CPU2
PS:需要注意需要确保启用TZ中断。此外，跳闸输入必须至少为3 * TBCLK的低电平，才足以trip
user5280439：
回复 Susan Yang:
谢谢您的回复！
Susan Yang：
回复 user5280439:
很高兴您能解决问题
