TI中文支持网麻烦帮忙分析下原因，单独运行28035的fir32的工程能够正常进入task1和task2
但是加入自己编写的大量文件后，无法进入CLA任务了，程序停留在Cla1ForceTask1andWait();
各位知道原因在哪里嘛？？？
Green Deng：
你好，请问你大概加入文件后做了哪些工作？最好测试一下两个程序在单步模式下运行有什么区别。
Cla1ForceTask1andWait 这个函数就是触发CLA任务，然后一直等待CLA执行完任务。如果你芯片一直停留在这里，那你就要看是不是CLA任务没有执行。注意CLA初始化。
user1937915：
回复 Green Deng:
原本的fir32的工程，CLA任务可以执行。后续添加其他文件后，CLA的配置未做任何改动，只是将原来CMD文件中，内存不够的地方做了调整，添加的文件是自行编写的用来做CANIICUART等模块的应用层函数文件。在原来没有结合的时候，单独的工程跑的CANIICUART这些功能都是正常的。放到一起后，就卡在Cla1ForceTask1andWait这个地方了。应该我的CLA的初始化配置都是一样的。
下面是我的CMD文件，我一直怀疑是CMD文件的问题，但是不知道如何下手：
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x300
-stack 0x300// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
// CLA_SCRATCHPAD_SIZE = 0x100;
–undef_sym=__cla_scratchpad_end
–undef_sym=__cla_scratchpad_startMEMORY
{
PAGE 0:/* Program Memory *//* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */RAML0: origin = 0x008000, length = 0x000800/* on-chip RAM block L0 */RAML1: origin = 0x008800, length = 0x000400/* on-chip RAM block L1 */OTP: origin = 0x3D7800, length = 0x000400/* on-chip OTP */
//FLASHH: origin = 0x3E8000, length = 0x002000/* on-chip FLASH */
//FLASHG: origin = 0x3EA000, length = 0x002000/* on-chip FLASH */FLASHF: origin = 0x3E8000, length = 0x002000/* on-chip FLASH */FLASHE: origin = 0x3EA000, length = 0x002000/* on-chip FLASH */FLASHD: origin = 0x3EC000, length = 0x002000/* on-chip FLASH */FLASHC: origin = 0x3EE000, length = 0x006000/* on-chip FLASH */FLASHA: origin = 0x3F6000, length = 0x001F80/* on-chip FLASH */CSM_RSVD: origin = 0x3F7F80, length = 0x000076/* Part of FLASHA.Program with all 0x0000 when CSM is in use. */BEGIN: origin = 0x3F7FF6, length = 0x000002/* Part of FLASHA.Used for "boot to Flash" bootloader mode. */CSM_PWL_P0: origin = 0x3F7FF8, length = 0x000008/* Part of FLASHA.CSM password locations in FLASHA */
IQTABLES: origin = 0x3FE000, length = 0x000B50/* IQ Math Tables in Boot ROM */IQTABLES2: origin = 0x3FEB50, length = 0x00008C/* IQ Math Tables in Boot ROM */IQTABLES3: origin = 0x3FEBDC, length = 0x0000AA/* IQ Math Tables in Boot ROM */
ROM: origin = 0x3FF27C, length = 0x000D44/* Boot ROM */RESET: origin = 0x3FFFC0, length = 0x000002/* part of boot ROM*/VECTORS: origin = 0x3FFFC2, length = 0x00003E/* part of boot ROM*/PAGE 1 :/* Data Memory *//* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation *//* Registers remain on PAGE1*/BOOT_RSVD: origin = 0x000000, length = 0x000050/* Part of M0, BOOT rom will use this for stack */RAMM0: origin = 0x000050, length = 0x0003B0/* on-chip RAM block M0 */RAMM1: origin = 0x000400, length = 0x000400/* on-chip RAM block M1 */RAML0: origin = 0x009000, length = 0x000800/* on-chip RAM block L0 */CLARAM0: origin = 0x009800, length = 0x000400CLARAM1: origin = 0x009C00, length = 0x000400
CLA1_MSGRAMLOW: origin = 0x001480, length = 0x000080CLA1_MSGRAMHIGH: origin = 0x001500, length = 0x000080FLASHB: origin = 0x3F4000, length = 0x002000/* on-chip FLASH */}
/* Allocate sections to memory blocks.Note:codestart user defined section in DSP28_CodeStartBranch.asm used to redirect codeexecution when booting to flashramfuncsuser defined section to store functions that will be copied from Flash into RAM
*/SECTIONS
{
/* Allocate program areas: */.cinit: > FLASHAPAGE = 0.pinit: > FLASHA,PAGE = 0.text: > FLASHCPAGE = 0codestart: > BEGINPAGE = 0ramfuncs: LOAD = FLASHD,RUN = RAML0,LOAD_START(_RamfuncsLoadStart),LOAD_SIZE(_RamfuncsLoadSize),RUN_START(_RamfuncsRunStart),PAGE = 0
csmpasswds: > CSM_PWL_P0PAGE = 0csm_rsvd: > CSM_RSVDPAGE = 0
/* Allocate uninitalized data sections: */.stack: > RAMM1PAGE = 1.cio: > RAML0PAGE = 1.sysmem: > RAMM1PAGE = 1.ebss: > RAML0PAGE = 1.esysmem: > RAML0PAGE = 1
/* Initalized sections go in Flash *//* For SDFlash to program these, they must be allocated to page 0 */.econst: > FLASHAPAGE = 0.switch: > FLASHAPAGE = 0/* Allocate IQ math areas: */IQmath: > FLASHAPAGE = 0/* Math Code */IQmathTables: > IQTABLES,PAGE = 0, TYPE = NOLOAD.bss_cla: > CLARAM1,PAGE = 1Cla1Prog: LOAD = FLASHD,RUN = RAML1,LOAD_START(_Cla1funcsLoadStart),LOAD_END(_Cla1funcsLoadEnd),RUN_START(_Cla1funcsRunStart),LOAD_SIZE(_Cla1funcsLoadSize),PAGE = 0Cla1ToCpuMsgRAM: > CLA1_MSGRAMLOW,PAGE = 1CpuToCla1MsgRAM: > CLA1_MSGRAMHIGH,PAGE = 1Cla1DataRam0: > CLARAM0,PAGE = 1Cla1DataRam1: > CLARAM1,PAGE = 1GROUP: LOAD = FLASHB,RUN = CLARAM1,LOAD_START(_Cla1mathTablesLoadStart),LOAD_END(_Cla1mathTablesLoadEnd),RUN_START(_Cla1mathTablesRunStart),LOAD_SIZE(_Cla1mathTablesLoadSize),PAGE = 1{CLA1mathTables.const_cla}CLAscratch: { *.obj(CLAscratch). += CLA_SCRATCHPAD_SIZE;*.obj(CLAscratch_end) } > CLARAM1,PAGE = 1/* Uncomment the section below if calling the IQNexp() or IQexp()functions from the IQMath.lib library in order to utilize therelevant IQ Math table in Boot ROM (This saves space and Boot ROMis 1 wait-state). If this section is not uncommented, IQmathTables2will be loaded into other memory (SARAM, Flash, etc.) and will takeup space, but 0 wait-state is possible.*//*IQmathTables2: > IQTABLES2, PAGE = 0, TYPE = NOLOAD{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}*//* Uncomment the section below if calling the IQNasin() or IQasin()functions from the IQMath.lib library in order to utilize therelevant IQ Math table in Boot ROM (This saves space and Boot ROMis 1 wait-state). If this section is not uncommented, IQmathTables2will be loaded into other memory (SARAM, Flash, etc.) and will takeup space, but 0 wait-state is possible.*//*IQmathTables3: > IQTABLES3, PAGE = 0, TYPE = NOLOAD{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}*/
/* .reset is a standard section used by the compiler.It contains the *//* the address of the start of _c_int00 for C Code./*/* When using the boot ROM this section and the CPU vector *//* table is not needed.Thus the default type is set here to*//* DSECT*/.reset: > RESET,PAGE = 0, TYPE = DSECTvectors: > VECTORSPAGE = 0, TYPE = DSECT}
user1937915：
回复 user1937915:
主程序如下：
#include "DSP28x_Project.h"// DSP28x Headerfile
#include "my_system.h"// my_System headerfile
#include "fir32_shared.h"// Include the test header file whose name is based on the test name
// which is defined by the macro TEST on the command line//Main Function
void main(void)
{//Step 1: Setup the system clock/*Disable the watchdog timer, initialize the system clock,*PLL and configure the peripheral clock.*/InitSysCtrl();
//Step 2: Initialize PIE control/*Initialize PIE control, disable all interrupts and* then copy over the PIE Vector table from BootROM to RAM*/DINT;InitPieCtrl();IER = 0x00000000;IFR = 0x00000000;InitPieVectTable();
/*Assign user defined ISR to the PIE vector table */EALLOW;PieVectTable.CLA1_INT1= &cla1_task1_isr;PieVectTable.CLA1_INT2= &cla1_task2_isr;PieVectTable.CLA1_INT3= &cla1_task3_isr;PieVectTable.CLA1_INT4= &cla1_task4_isr;PieVectTable.CLA1_INT5= &cla1_task5_isr;PieVectTable.CLA1_INT6= &cla1_task6_isr;PieVectTable.CLA1_INT7= &cla1_task7_isr;PieVectTable.CLA1_INT8= &cla1_task8_isr;EDIS;//Copy over the CLA code and Tablesmemcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadSize);memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32)&Cla1mathTablesLoadSize);/*Compute all CLA task vectors */EALLOW;Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1 – (Uint32)&Cla1Prog_Start);Cla1Regs.MVECT2 = (Uint16)((Uint32)&Cla1Task2 – (Uint32)&Cla1Prog_Start);Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3 – (Uint32)&Cla1Prog_Start);Cla1Regs.MVECT4 = (Uint16)((Uint32)&Cla1Task4 – (Uint32)&Cla1Prog_Start);Cla1Regs.MVECT5 = (Uint16)((Uint32)&Cla1Task5 – (Uint32)&Cla1Prog_Start);Cla1Regs.MVECT6 = (Uint16)((Uint32)&Cla1Task6 – (Uint32)&Cla1Prog_Start);Cla1Regs.MVECT7 = (Uint16)((Uint32)&Cla1Task7 – (Uint32)&Cla1Prog_Start);Cla1Regs.MVECT8 = (Uint16)((Uint32)&Cla1Task8 – (Uint32)&Cla1Prog_Start);EDIS;//Step 3 : Mapping CLA tasks/*All tasks are enabled and will be started by an ePWM trigger*Map CLA program memory to the CLA and enable software breakpoints*/EALLOW;//Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_ADCINT1;// ADCINT1 starts Task 1Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE;Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_NONE;Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_NONE;Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_NONE;Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_NONE;Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_NONE;Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_NONE;Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE;Cla1Regs.MIER.all = 0x00FF;EDIS;PieCtrlRegs.PIEIER11.bit.INTx1 = 1;/*Enable CLA interrupts at the group and subgroup levels *///PieCtrlRegs.PIEIER11.all = 0xFFFF;IER |= M_INT11;EINT;// Enable Global interrupt INTMERTM;// Enable Global realtime interrupt DBGM/* Switch the CLA program space to the CLA and enable software forcing* Also switch over CLA data ram 0 and 1*/EALLOW;Cla1Regs.MMEMCFG.bit.PROGE = 1;Cla1Regs.MCTL.bit.IACKE = 1;Cla1Regs.MMEMCFG.bit.RAM0E = CLARAM0_ENABLE;Cla1Regs.MMEMCFG.bit.RAM1E = CLARAM1_ENABLE;EDIS;g_uiClaRtIn_V = 1000;g_uiClaRtOut_V = 1000;g_uiClaRtOut_I = 1000;g_uiClaRtAvg_I = 1000;Cla1ForceTask1andWait();// 启动任务2，用于初始化RAM区的变量值EALLOW;Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_ADCINT1;// ADCINT1 starts Task 1EDIS;Adc_init();// ADC初始化EPwm_Init();// PWM初始化EALLOW;/*PWM1设置为输出，并且为低*/GpioDataRegs.GPASET.bit.GPIO23 = 1;// IO口，输出为低GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0;// Configure GPIO0GpioCtrlRegs.GPADIR.bit.GPIO23 = 1;// 设置方向为输出GpioDataRegs.GPASET.bit.GPIO23 = 1;EDIS;// Invoke Task(s)while(1){test_run();//if(GpioDataRegs.GPADAT.bit.GPIO23 == 0)
//{
//GpioDataRegs.GPASET.bit.GPIO23 = 1;// IO口，输出为低
//}
//else
//{
//GpioDataRegs.GPACLEAR.bit.GPIO23 = 1;// IO口，输出为低
//}
delay_10us(1);}
}数据定义文件：
#include "DSP28x_Project.h"
#include "DSP2803x_Cla_defines.h"
// Include the test header file whose name is based on the test name
// which is defined by the macro TEST on the command line
#include "fir32_shared.h"//GLobal Data
//Ensure that all data is placed in the data rams//Task 1 (C) Variables
#pragma DATA_SECTION(g_uiClaRtIn_V, "CpuToCla1MsgRAM");
Uint32 g_uiClaRtIn_V;
#pragma DATA_SECTION(g_uiClaRtOut_V, "CpuToCla1MsgRAM");
Uint32 g_uiClaRtOut_V;
#pragma DATA_SECTION(g_uiClaRtOut_I, "CpuToCla1MsgRAM");
Uint32 g_uiClaRtOut_I;
#pragma DATA_SECTION(g_uiClaRtAvg_I, "CpuToCla1MsgRAM");
Uint32 g_uiClaRtAvg_I;#pragma DATA_SECTION(g_uiClaIn_V,"Cla1ToCpuMsgRAM");
int32 g_uiClaIn_V;// 输入电压
#pragma DATA_SECTION(g_uiClaOut_V,"Cla1ToCpuMsgRAM");
int32 g_uiClaOut_V;// 输出电流
#pragma DATA_SECTION(g_uiClaOut_I,"Cla1ToCpuMsgRAM");
int32 g_uiClaOut_I;// 输出电流
#pragma DATA_SECTION(g_uiClaAvg_I,"Cla1ToCpuMsgRAM");
int32 g_uiClaAvg_I;// 输出平均电流//Task 2 (C) Variables
//Task 3 (C) Variables
//Task 4 (C) Variables
//Task 5 (C) Variables
//Task 6 (C) Variables
//Task 7 (C) Variables
//Task 8 (C) Variables
//Common (C) Variables
void test_run(void)
{int i;for(i=0;i<10;i++){
//Cla1ForceTask1andWait();//Cla1ForceTask2andWait();}
#if 0Cla1ForceTask2andWait();
Cla1ForceTask3andWait();
Cla1ForceTask4andWait();
Cla1ForceTask5andWait();
Cla1ForceTask6andWait();
Cla1ForceTask7andWait();
Cla1ForceTask8andWait();
#endif
}//###########################################################################
// CLA ISRs
//###########################################################################
__interrupt void cla1_task1_isr( void)
{AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;// Clear ADCINT1 flag reinitialize for next SOCPieCtrlRegs.PIEACK.all = 0xFFFF;
if(GpioDataRegs.GPADAT.bit.GPIO23 == 0){GpioDataRegs.GPASET.bit.GPIO23 = 1;// IO口，输出为低}else{GpioDataRegs.GPACLEAR.bit.GPIO23 = 1;// IO口，输出为低}
}__interrupt void cla1_task2_isr( void)
{PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}__interrupt void cla1_task3_isr( void)
{PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}__interrupt void cla1_task4_isr( void)
{PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}__interrupt void cla1_task5_isr( void)
{PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}__interrupt void cla1_task6_isr( void)
{PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}__interrupt void cla1_task7_isr( void)
{PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}__interrupt void cla1_task8_isr( void)
{PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}头文件：
#ifndef FIR32_SHARED_H_
#define FIR32_SHARED_H_#ifdef __cplusplus
extern "C" {
#endif//Task 1 (C) Variables
#define FILTER_LEN5
#define INPUT_LEN128
#define OUTPUT_LENINPUT_LEN+FILTER_LEN#define CLARAM0_ENABLE1
#define CLARAM1_ENABLE1#define HARDWARE 1
// Constants
#define OSCCLK(10000000UL)// < Internal OSC frequency
//#define SYSCLK(60000000UL)// < System Clock frequency
#define PER_CLK_DIV(4)// < Low speed peripheral clock dividers
#define PER_CLK(SYSCLK/PER_CLK_DIV)// < Low speed peripheral clock
#define DIV_SEL(2)// < Clock divider selection
#define CLK_DIV((SYSCLK * DIV_SEL)/OSCCLK)// < Clock dividerextern int32 g_uiClaIn_V;// 输入电压
extern int32 g_uiClaOut_V;// 输出电流
extern int32 g_uiClaOut_I;// 输出电流
extern int32 g_uiClaAvg_I;// 输出平均电流extern Uint32 g_uiClaRtIn_V;
extern Uint32 g_uiClaRtOut_V;
extern Uint32 g_uiClaRtOut_I;
extern Uint32 g_uiClaRtAvg_I;//CLA ISRs
__interrupt void cla1_task1_isr( void );
__interrupt void cla1_task2_isr( void );
__interrupt void cla1_task3_isr( void );
__interrupt void cla1_task4_isr( void );
__interrupt void cla1_task5_isr( void );
__interrupt void cla1_task6_isr( void );
__interrupt void cla1_task7_isr( void );
__interrupt void cla1_task8_isr( void );//Linker defined vars
extern Uint16 Cla1Prog_Start;
extern Uint16 Cla1funcsLoadStart;
extern Uint16 Cla1funcsLoadEnd;
extern Uint16 Cla1funcsRunStart;
extern Uint16 Cla1funcsLoadSize;
extern Uint16 Cla1mathTablesLoadStart;
extern Uint16 Cla1mathTablesRunStart;
extern Uint16 Cla1mathTablesLoadSize;//Task 2 (C) Variables
//Task 3 (C) Variables
//Task 4 (C) Variables
//Task 5 (C) Variables
//Task 6 (C) Variables
//Task 7 (C) Variables
//Task 8 (C) Variables
//Common (C) Variables
//CLA C Tasks
__interrupt void Cla1Task1();
__interrupt void Cla1Task2();
__interrupt void Cla1Task3();
__interrupt void Cla1Task4();
__interrupt void Cla1Task5();
__interrupt void Cla1Task6();
__interrupt void Cla1Task7();
__interrupt void Cla1Task8();//C Function Prototypes
void test_run();
void test_report();#ifdef __cplusplus
}
#endif /* extern "C" */#endif /*FIR32_SHARED_H_*/
CLA文件
#include "DSP28x_Project.h"
// Include the test header file whose name is based on the test name
// which is defined by the macro TEST on the command line
#include "fir32_shared.h"// fir32_shared library headerfile
#include "my_system.h"// my_System headerfile//Task 1 : {FILTER_LEN} tap lowpass FIR filter
__interrupt void Cla1Task1 ( void )
{float fdata = 0;//__mdebugstop();// 计算采样值fdata = (AdcResult.ADCRESULT10 + AdcResult.ADCRESULT11)>>1;fdata = AdcResult.ADCRESULT10;g_uiClaIn_V = (float)g_uiClaRtIn_V * fdata * 0.001;fdata = (AdcResult.ADCRESULT0 + AdcResult.ADCRESULT1 + AdcResult.ADCRESULT2 + AdcResult.ADCRESULT3)>>2;fdata = (float)AdcResult.ADCRESULT0;g_uiClaOut_V = (float)g_uiClaRtOut_V * fdata * 0.001;fdata = (AdcResult.ADCRESULT4 + AdcResult.ADCRESULT5 + AdcResult.ADCRESULT6 + AdcResult.ADCRESULT7)>>2;fdata = (float)AdcResult.ADCRESULT4;g_uiClaOut_I = (float)g_uiClaRtOut_I * fdata * 0.001;fdata = (AdcResult.ADCRESULT8 + AdcResult.ADCRESULT9)>>1;fdata = (float)AdcResult.ADCRESULT8;g_uiClaAvg_I = (float)g_uiClaRtAvg_I * fdata * 0.001;
}__interrupt void Cla1Task2 ( void )
{g_uiClaIn_V = 1;g_uiClaOut_V = 1;g_uiClaOut_I = 1;g_uiClaAvg_I = 1;
}__interrupt void Cla1Task3 ( void )
{
}__interrupt void Cla1Task4 ( void )
{
}__interrupt void Cla1Task5 ( void )
{
}__interrupt void Cla1Task6 ( void )
{
}__interrupt void Cla1Task7 ( void )
{
}__interrupt void Cla1Task8 ( void )
{
}
user1937915：
回复 user1937915:
生成的.map文件
******************************************************************************TMS320C2000 Linker PC v15.12.1
******************************************************************************
>> Linked Thu Aug 13 17:43:06 2020OUTPUT FILE NAME:<DCDC_Cla.out>
ENTRY POINT SYMBOL: "code_start"address: 003f7ff6MEMORY CONFIGURATION
nameoriginlengthusedunusedattrfill
——————————————————————-
PAGE 0:RAML000008000000008000000044a000003b6RWIXRAML10000880000000400000000b000000350RWIXOTP003d7800000004000000000000000400RWIXFLASHF003e8000000020000000000000002000RWIXFLASHE003ea000000020000000000000002000RWIXFLASHD003ec00000002000000004fa00001b06RWIXFLASHC003ee0000000600000002d0a000032f6RWIXFLASHA003f600000001f800000033c00001c44RWIXCSM_RSVD003f7f80000000760000000000000076RWIXBEGIN003f7ff6000000020000000200000000RWIXCSM_PWL_P0003f7ff8000000080000000000000008RWIXIQTABLES003fe00000000b500000000000000b50RWIXIQTABLES2003feb500000008c000000000000008cRWIXIQTABLES3003febdc000000aa00000000000000aaRWIXROM003ff27c00000d440000000000000d44RWIXRESET003fffc0000000020000000000000002RWIXVECTORS003fffc20000003e000000000000003eRWIXPAGE 1:BOOT_RSVD00000000000000500000000000000050RWIXRAMM000000050000003b000000000000003b0RWIXRAMM100000400000004000000030000000100RWIXDEV_EMU00000880000001050000000400000101RWIXSYS_PWR_CTL00000985000000030000000300000000RWIXFLASH_REGS00000a80000000600000000800000058RWIXCSM00000ae0000000100000001000000000RWIXADC_RESULT00000b00000000200000002000000000RWIXCPU_TIMER000000c00000000080000000800000000RWIXCPU_TIMER100000c08000000080000000800000000RWIXCPU_TIMER200000c10000000080000000800000000RWIXPIE_CTRL00000ce0000000200000001a00000006RWIXPIE_VECT00000d00000001000000010000000000RWIXCLA100001400000000800000004000000040RWIXCLA1_MSGRAMLOW00001480000000800000000800000078RWIXCLA1_MSGRAMHIGH00001500000000800000000800000078RWIXECANA0000600000000040000000340000000cRWIXECANA_LAM00006040000000400000004000000000RWIXECANA_MOTS00006080000000400000004000000000RWIXECANA_MOTO000060c0000000400000004000000000RWIXECANA_MBOX00006100000001000000010000000000RWIXCOMP10000640000000020000000140000000cRWIXCOMP20000642000000020000000140000000cRWIXCOMP30000644000000020000000140000000cRWIXEPWM100006800000000400000004000000000RWIXEPWM200006840000000400000004000000000RWIXEPWM300006880000000400000004000000000RWIXEPWM4000068c0000000400000004000000000RWIXEPWM500006900000000400000004000000000RWIXEPWM600006940000000400000004000000000RWIXEPWM700006980000000400000004000000000RWIXECAP100006a00000000200000002000000000RWIXHRCAP100006ac0000000200000002000000000RWIXHRCAP200006ae0000000200000002000000000RWIXEQEP100006b00000000400000004000000000RWIXLINA00006c00000000800000004a00000036RWIXGPIOCTRL00006f80000000400000004000000000RWIXGPIODAT00006fc0000000200000002000000000RWIXGPIOINT00006fe0000000200000000c00000014RWIXSYSTEM00007010000000200000002000000000RWIXSPIA00007040000000100000001000000000RWIXSCIA00007050000000100000001000000000RWIXNMIINTRUPT00007060000000100000001000000000RWIXXINTRUPT00007070000000100000001000000000RWIXADC00007100000000800000005000000030RWIXSPIB00007740000000100000001000000000RWIXI2CA0000790000000040000000220000001eRWIXRAML000009000000008000000037c00000484RWIXCLARAM000009800000004000000000000000400RWIXCLARAM100009c00000004000000010000000300RWIXPARTID003d7e80000000010000000100000000RWIXFLASHB003f4000000020000000000000002000RWIXCSM_PWL003f7ff8000000080000000800000000RWIX
SECTION ALLOCATION MAP
outputattributes/
sectionpageoriginlengthinput sections
————————————————
ramfuncs0003ec0000000044aRUN ADDR = 00008000003ec0000000042cmy_System.obj (ramfuncs)003ec42c0000001amy_Time0.obj (ramfuncs:retain)003ec44600000004DSP2803x_usDelay.obj (ramfuncs)Cla1Prog0003ec44a000000b0RUN ADDR = 00008800003ec44a00000060fir32.obj (Cla1Prog:_Cla1Task1)003ec4aa00000020fir32.obj (Cla1Prog:_Cla1Task2)003ec4ca00000008fir32.obj (Cla1Prog:_Cla1Task3)003ec4d200000008fir32.obj (Cla1Prog:_Cla1Task4)003ec4da00000008fir32.obj (Cla1Prog:_Cla1Task5)003ec4e200000008fir32.obj (Cla1Prog:_Cla1Task6)003ec4ea00000008fir32.obj (Cla1Prog:_Cla1Task7)003ec4f200000008fir32.obj (Cla1Prog:_Cla1Task8)
.text0003ee00000002d0a003ee00000000c1cmy_System.obj (.text)003eec1c0000082amy_can.obj (.text)003ef44600000342my_Adc.obj (.text)003ef788000002bcmy_I2C.obj (.text)003efa4400000280my_pwm.obj (.text)003efcc400000270my_sci.obj (.text)003eff34000001d4DSP2803x_Adc.obj (.text)003f01080000017cDSP2803x_DefaultIsr.obj (.text:retain)003f028400000147DSP2803x_SysCtrl.obj (.text)003f03cb00000142SFO_TI_Build_V6.lib : SFO.obj (.text)003f050d00000119my_Time0.obj (.text)003f0626000000e6main.obj (.text)003f070c000000d6DSP2803x_EPwm.obj (.text)003f07e200000083rts2800_ml.lib : fs_div.obj (.text)003f08650000007bmy_Time0.obj (.text:retain)003f08e000000078rts2800_ml.lib : fs_add.obj (.text)003f09580000005a: fs_mpy.obj (.text)003f09b200000059fir32_shared_data.obj (.text:retain)003f0a0b00000054my_ECAP.obj (.text:retain)003f0a5f00000054rts2800_ml.lib : boot.obj (.text)003f0ab300000053my_Gpio.obj (.text)003f0b0600000046rts2800_ml.lib : cpy_tbl.obj (.text)003f0b4c0000002a: l_div.obj (.text)003f0b7600000029: exit.obj (.text)003f0b9f00000029: fs_tol.obj (.text)003f0bc800000028DSP2803x_PieCtrl.obj (.text)003f0bf000000026my_sci.obj (.text:retain)003f0c1600000025rts2800_ml.lib : fs_toi.obj (.text)003f0c3b00000022my_can.obj (.text:retain)003f0c5d0000001drts2800_ml.lib : memcpy.obj (.text)003f0c7a0000001a: cpy_utils.obj (.text)003f0c9400000019: args_main.obj (.text)003f0cad00000011DSP2803x_PieVect.obj (.text)003f0cbe00000010rts2800_ml.lib : u_tofs.obj (.text)003f0cce0000000fmy_Adc.obj (.text:retain)003f0cdd0000000dmy_pwm.obj (.text:retain)003f0cea0000000brts2800_ml.lib : u_div.obj (.text)003f0cf500000009: _lock.obj (.text)003f0cfe00000008DSP2803x_CodeStartBranch.obj (.text)003f0d0600000002rts2800_ml.lib : pre_init.obj (.text)003f0d0800000001fir32_shared_data.obj (.text)003f0d0900000001rts2800_ml.lib : startup.obj (.text)
.cinit0003f60000000023c003f6000000000e3my_System.obj (.cinit)003f60e300000065my_Adc.obj (.cinit)003f614800000062my_Time0.obj (.cinit)003f61aa00000033my_pwm.obj (.cinit)003f61dd00000024my_sci.obj (.cinit)003f620100000013my_can.obj (.cinit)003f62140000000erts2800_ml.lib : exit.obj (.cinit)003f62220000000amy_ECAP.obj (.cinit)003f622c00000005rts2800_ml.lib : _lock.obj (.cinit:__lock)003f623100000005: _lock.obj (.cinit:__unlock)003f623600000004SFO_TI_Build_V6.lib : SFO.obj (.cinit)003f623a00000002–HOLE– [fill = 0]
.econst0003f623c00000100003f623c00000100DSP2803x_PieVect.obj (.econst:_PieVectTableInit)
codestart
*0003f7ff600000002003f7ff600000002DSP2803x_CodeStartBranch.obj (codestart).stack10000040000000300UNINITIALIZED0000040000000300–HOLE–
user1937915：
回复 user1937915:
生成的.map文件
******************************************************************************TMS320C2000 Linker PC v15.12.1
******************************************************************************
>> Linked Thu Aug 13 17:43:06 2020OUTPUT FILE NAME:<DCDC_Cla.out>
ENTRY POINT SYMBOL: "code_start"address: 003f7ff6MEMORY CONFIGURATION
nameoriginlengthusedunusedattrfill
——————————————————————-
PAGE 0:RAML000008000000008000000044a000003b6RWIXRAML10000880000000400000000b000000350RWIXOTP003d7800000004000000000000000400RWIXFLASHF003e8000000020000000000000002000RWIXFLASHE003ea000000020000000000000002000RWIXFLASHD003ec00000002000000004fa00001b06RWIXFLASHC003ee0000000600000002d0a000032f6RWIXFLASHA003f600000001f800000033c00001c44RWIXCSM_RSVD003f7f80000000760000000000000076RWIXBEGIN003f7ff6000000020000000200000000RWIXCSM_PWL_P0003f7ff8000000080000000000000008RWIXIQTABLES003fe00000000b500000000000000b50RWIXIQTABLES2003feb500000008c000000000000008cRWIXIQTABLES3003febdc000000aa00000000000000aaRWIXROM003ff27c00000d440000000000000d44RWIXRESET003fffc0000000020000000000000002RWIXVECTORS003fffc20000003e000000000000003eRWIXPAGE 1:BOOT_RSVD00000000000000500000000000000050RWIXRAMM000000050000003b000000000000003b0RWIXRAMM100000400000004000000030000000100RWIXDEV_EMU00000880000001050000000400000101RWIXSYS_PWR_CTL00000985000000030000000300000000RWIXFLASH_REGS00000a80000000600000000800000058RWIXCSM00000ae0000000100000001000000000RWIXADC_RESULT00000b00000000200000002000000000RWIXCPU_TIMER000000c00000000080000000800000000RWIXCPU_TIMER100000c08000000080000000800000000RWIXCPU_TIMER200000c10000000080000000800000000RWIXPIE_CTRL00000ce0000000200000001a00000006RWIXPIE_VECT00000d00000001000000010000000000RWIXCLA100001400000000800000004000000040RWIXCLA1_MSGRAMLOW00001480000000800000000800000078RWIXCLA1_MSGRAMHIGH00001500000000800000000800000078RWIXECANA0000600000000040000000340000000cRWIXECANA_LAM00006040000000400000004000000000RWIXECANA_MOTS00006080000000400000004000000000RWIXECANA_MOTO000060c0000000400000004000000000RWIXECANA_MBOX00006100000001000000010000000000RWIXCOMP10000640000000020000000140000000cRWIXCOMP20000642000000020000000140000000cRWIXCOMP30000644000000020000000140000000cRWIXEPWM100006800000000400000004000000000RWIXEPWM200006840000000400000004000000000RWIXEPWM300006880000000400000004000000000RWIXEPWM4000068c0000000400000004000000000RWIXEPWM500006900000000400000004000000000RWIXEPWM600006940000000400000004000000000RWIXEPWM700006980000000400000004000000000RWIXECAP100006a00000000200000002000000000RWIXHRCAP100006ac0000000200000002000000000RWIXHRCAP200006ae0000000200000002000000000RWIXEQEP100006b00000000400000004000000000RWIXLINA00006c00000000800000004a00000036RWIXGPIOCTRL00006f80000000400000004000000000RWIXGPIODAT00006fc0000000200000002000000000RWIXGPIOINT00006fe0000000200000000c00000014RWIXSYSTEM00007010000000200000002000000000RWIXSPIA00007040000000100000001000000000RWIXSCIA00007050000000100000001000000000RWIXNMIINTRUPT00007060000000100000001000000000RWIXXINTRUPT00007070000000100000001000000000RWIXADC00007100000000800000005000000030RWIXSPIB00007740000000100000001000000000RWIXI2CA0000790000000040000000220000001eRWIXRAML000009000000008000000037c00000484RWIXCLARAM000009800000004000000000000000400RWIXCLARAM100009c00000004000000010000000300RWIXPARTID003d7e80000000010000000100000000RWIXFLASHB003f4000000020000000000000002000RWIXCSM_PWL003f7ff8000000080000000800000000RWIX
SECTION ALLOCATION MAP
outputattributes/
sectionpageoriginlengthinput sections
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ramfuncs0003ec0000000044aRUN ADDR = 00008000003ec0000000042cmy_System.obj (ramfuncs)003ec42c0000001amy_Time0.obj (ramfuncs:retain)003ec44600000004DSP2803x_usDelay.obj (ramfuncs)Cla1Prog0003ec44a000000b0RUN ADDR = 00008800003ec44a00000060fir32.obj (Cla1Prog:_Cla1Task1)003ec4aa00000020fir32.obj (Cla1Prog:_Cla1Task2)003ec4ca00000008fir32.obj (Cla1Prog:_Cla1Task3)003ec4d200000008fir32.obj (Cla1Prog:_Cla1Task4)003ec4da00000008fir32.obj (Cla1Prog:_Cla1Task5)003ec4e200000008fir32.obj (Cla1Prog:_Cla1Task6)003ec4ea00000008fir32.obj (Cla1Prog:_Cla1Task7)003ec4f200000008fir32.obj (Cla1Prog:_Cla1Task8)
.text0003ee00000002d0a003ee00000000c1cmy_System.obj (.text)003eec1c0000082amy_can.obj (.text)003ef44600000342my_Adc.obj (.text)003ef788000002bcmy_I2C.obj (.text)003efa4400000280my_pwm.obj (.text)003efcc400000270my_sci.obj (.text)003eff34000001d4DSP2803x_Adc.obj (.text)003f01080000017cDSP2803x_DefaultIsr.obj (.text:retain)003f028400000147DSP2803x_SysCtrl.obj (.text)003f03cb00000142SFO_TI_Build_V6.lib : SFO.obj (.text)003f050d00000119my_Time0.obj (.text)003f0626000000e6main.obj (.text)003f070c000000d6DSP2803x_EPwm.obj (.text)003f07e200000083rts2800_ml.lib : fs_div.obj (.text)003f08650000007bmy_Time0.obj (.text:retain)003f08e000000078rts2800_ml.lib : fs_add.obj (.text)003f09580000005a: fs_mpy.obj (.text)003f09b200000059fir32_shared_data.obj (.text:retain)003f0a0b00000054my_ECAP.obj (.text:retain)003f0a5f00000054rts2800_ml.lib : boot.obj (.text)003f0ab300000053my_Gpio.obj (.text)003f0b0600000046rts2800_ml.lib : cpy_tbl.obj (.text)003f0b4c0000002a: l_div.obj (.text)003f0b7600000029: exit.obj (.text)003f0b9f00000029: fs_tol.obj (.text)003f0bc800000028DSP2803x_PieCtrl.obj (.text)003f0bf000000026my_sci.obj (.text:retain)003f0c1600000025rts2800_ml.lib : fs_toi.obj (.text)003f0c3b00000022my_can.obj (.text:retain)003f0c5d0000001drts2800_ml.lib : memcpy.obj (.text)003f0c7a0000001a: cpy_utils.obj (.text)003f0c9400000019: args_main.obj (.text)003f0cad00000011DSP2803x_PieVect.obj (.text)003f0cbe00000010rts2800_ml.lib : u_tofs.obj (.text)003f0cce0000000fmy_Adc.obj (.text:retain)003f0cdd0000000dmy_pwm.obj (.text:retain)003f0cea0000000brts2800_ml.lib : u_div.obj (.text)003f0cf500000009: _lock.obj (.text)003f0cfe00000008DSP2803x_CodeStartBranch.obj (.text)003f0d0600000002rts2800_ml.lib : pre_init.obj (.text)003f0d0800000001fir32_shared_data.obj (.text)003f0d0900000001rts2800_ml.lib : startup.obj (.text)
.cinit0003f60000000023c003f6000000000e3my_System.obj (.cinit)003f60e300000065my_Adc.obj (.cinit)003f614800000062my_Time0.obj (.cinit)003f61aa00000033my_pwm.obj (.cinit)003f61dd00000024my_sci.obj (.cinit)003f620100000013my_can.obj (.cinit)003f62140000000erts2800_ml.lib : exit.obj (.cinit)003f62220000000amy_ECAP.obj (.cinit)003f622c00000005rts2800_ml.lib : _lock.obj (.cinit:__lock)003f623100000005: _lock.obj (.cinit:__unlock)003f623600000004SFO_TI_Build_V6.lib : SFO.obj (.cinit)003f623a00000002–HOLE– [fill = 0]
.econst0003f623c00000100003f623c00000100DSP2803x_PieVect.obj (.econst:_PieVectTableInit)
codestart
*0003f7ff600000002003f7ff600000002DSP2803x_CodeStartBranch.obj (codestart).stack10000040000000300UNINITIALIZED0000040000000300–HOLE–
Green Deng：
不好意思，这个内容实在有点太多了，我这边给两个建议你参考一下：
1、用官方提供的cmd文件测试一下，C:\ti\c2000\C2000Ware_3_02_00_00\device_support\f2803x\common\cmd
2、在CLA中设置断点指令，看一下具体是卡在那句程序上
user1937915：
回复 Green Deng:
我采用的就是系统自带的CMD文件，但是由于加入代码后，CMD部分的内存区域不够了，所以对CMD做了适当修改。经过一步步的对比调试，发现存在两个CMD文件问题：
1、定义个ramfuncs和Cla1Prog的RAM区域，Cla1Prog需要定义为0x9000开头，ramfuncs定位为0x9800开头；则CLA的任务模块就能够正常运行，反之则不能正常运行CLA任务。
2、按照第1的方式，更改好之后，发现还存在一个问题，就是我把部分的函数从FLASH搬运到RAM区域进行执行，结果发现，只要调用了这个#pragma CODE_SECTION里面的函数，程序就会跑飞到这个非法中断__interrupt void ILLEGAL_ISR(void)。第2个问题，我始终没有找到原因，麻烦帮忙分析下。首先在普通的程序里面，#pragma CODE_SECTION里面的函数是没有问题的。在fir32里面CLA也是没有问题的；合起来之后现在就存在第2点问题。无论怎么更改ramfuncs的RAM地址定义，好像都没有用，问题还是存在？
拜托各位大神了
