TI中文支持网请问 McASP + DMA 多通道AXR输出，有参考例程吗或如何配置？ 实现如图的功能。
Tony Tang：
23.2.4.3.2 Transfers through the DMA PortCAUTIONTo perform internal transfers through the DMA port, clear XBUSEL/RBUSEL bitto 0 in the respective XFMT/RFMT registers. Failure to do so will result insoftware malfunction.Typically, you will access the McASP XRBUF registers through the DMA port. To access through the DMAport, simply have the CPU or DMA access the XRBUF through its DMA port location. See yourdevice-specific data manual for the exact memory address. Through the DMA port, the DMA/CPU canservice all the serializers through a single address. The McASP automatically cycles through theappropriate serializers.For transmit operations through the DMA port, the DMA/CPU should write to the same XBUF DMA portaddress to service all of the active transmit serializers. In addition, the DMA/CPU should write to the XBUFfor all active transmit serializers in incremental (although not necessarily consecutive) order. For example,if serializers 0, 4, 5, and 7 are set up as active transmitters, the DMA/CPU should write to the XBUF DMAport address four times with data for serializers 0, 4, 5, and 7 upon each transmit data ready event. Thisexact servicing order must be followed so that data appears in the appropriate serializers.Similarly, for receive operations through the DMA port, the DMA/CPU should read from the same RBUFDMA port address to service all of the active receive serializers. In addition, reads from the active receiveserializers through the DMA port return data in incremental (although not necessarily consecutive) order.For example, if serializers 1, 2, 3, and 6 are set up as active receivers, the DMA/CPU should read fromthe RBUF DMA port address four times to obtain data for serializers 1, 2, 3, and 6 in this exact order,upon each receive data ready event.When transmitting, the DMA/CPU must write data to each serializer configured as "active" and "transmit"within each time slot. Failure to do so results in a buffer underrun condition (Section 23.2.4.7.2). Similarly,when receiving, data must be read from each serializer configured as "active" and "receive" within eachtime slot. Failure to do results in a buffer overrun condition (Section 23.2.4.7.3).To perform internal transfers through the DMA port, clear XBUSEL/RBUSEL bit to 0 in the respectiveXFMT/RFMT registers.
