TI中文支持网ni好，我用6455pll设置emif时钟。pll输入是50M，倍频20，然后div4分频为8，此时emif输入时钟应为1000/8=125M，但是为什么用示波器测量emif输入时钟是62.5M？
pll代码：
int PLLM_val = 20;
//int PREDIV_val = 1;
int PLLDIV4_val = 8;
int PLLDIV5_val = 4;
CSR &=~(0x1);// /* Control Status Register */关中断
PLLCTL_1 &= ~(0x00000020);//write PLLENSRC = 0 (enable PLLEN bit).
PLLCTL_1 &= ~(0x00000001);//write PLLEN = 0 (bypass mode).
for (i=0 ; i<100 ; i++);//Wait 4 cycles of the slowest of PLLOUT or reference clock source (CLKIN).
PLLCTL_1 |= 0x00000008;//write PLLRST = 1 (PLL is reset).
PLLM_1 = PLLM_val – 1;//设置倍频的值
//PREDIV_1 = (PREDIV_val – 1) | 0x8000;//设置预分频值,打开预分频使能
PREDIV_1 =0x8000;
while( (PLLSTAT_1 ) & 0x00000001);//GOSTAT=0;GO operation is not in progress. SYSCLK divide ratios are not being changed.
PLLDIV4_1 = (PLLDIV4_val – 1) | 0x8000;
PLLCMD_1 |= 0x00000001;//Initiates GO operation.
while( (PLLSTAT_1) & 0x00000001);
PLLDIV5_1 = (PLLDIV5_val – 1) | 0x8000;
PLLCMD_1 |= 0x00000001;//Initiates GO operation.
while( (PLLSTAT_1) & 0x00000001);
for (i=0 ; i<1000 ; i++);
PLLCTL_1 &= ~(0x00000008);//write PLLRST = 0 to bring PLL out of reset.
for (i=0 ; i<4000 ; i++);//Wait for PLL to lock
PLLCTL_1 |= (0x00000001);//write PLLEN = 1 to enable PLL mode
PERLOCK = 0x0f0a0b00;
PERCFG0 = 0xC0555555;
PERCFG1 = 0x3;
CSR |= 0x1;
ISTP = 0x00800000;
以上标红的是什么意思？
还有，我的emif接的ce4，想访问sbsram(CY7C1380C)，取数放数都测过，均正确。用1ms中断计时（ms中断测量过，1min进60000次中断）。为什么我分别用实测的125M emif时钟个实测的62.5M时钟计时，放完2M个int数分别用时44ms和42ms?时间应该差一倍啊
VEC : o = 0x00800000, l = 0x00000200
PRAM : o = 0x00800200, l = 0x000ffc00
BRAM : o = 0x00900000, l = 0x00100000 /* Internal L2 RAM */
L1PRAM: o = 0x00E00000 l = 0x00008000 /* 32kB L1 Program SRAM/CACHE */ L1DRAM: o = 0x00F00000 l = 0x00008000 /* 32kB L1 Data SRAM/CACHE */
EMIFA_CE2: o = 0xA0000000 l = 0x00800000 /* 8MB EMIFA CE2-FPGA */
EMIFA_CE3: o = 0xB0000000 l = 0x00800000 /* 8MB EMIFA CE3-FLASH */
EMIFA_CE4: o = 0xC0000000 l = 0x00800000 /* 8MB EMIFA CE4-SBSRAM*/
EMIFA_CE5: o = 0xD0000000 l = 0x00800000 /* 8MB EMIFA CE5-FPGA */
DDR2_CE0: o = 0xE0000000 l = 0x10000000 /* 512MB EMIFB CE0 */
void EMIFA_INIT(void)
{
EMIFA_CFG_BPRIO = 0x000000FF;
EMIFA_CFG_CE2CFG = 0x8000030A;
EMIFA_CFG_CE3CFG = 0x0FFFFFFC;
EMIFA_CFG_CE4CFG = 0x8000000A;
EMIFA_CFG_CE5CFG = 0x0FFFFFFC;
}
哪里可能有问题，急求。
user4345686：
回复 Shine:
谢谢，前两点明白了。
第三点，用1us中断计时（us中断测量过，1min进60000000次中断）。写1个数据都是3um。我试了，向片内L2 RAM存0x1000个int和向片外sbsram存0x1000个int数，花费的时间都是81us,是不是就能断定片内片外的时钟是用的1个？
那么就是不是说明我配置的pll有问题？但是我查了N遍了，是按照手册上配置的啊，就是上面贴的pll配置程序，您能帮我看一下哪有问题吗？
或者还有哪里可能有问题？
user4345686：
回复 Shine:
谢谢谢谢，我大概是知道了。
