工程师,您好!我在进行C6678开发的时候,在编写CMD文件时遇到一些疑问想向您确认一下,目前我们拟采用单核也就是core0进行开发,也不打算用SL2这段共享内存,在与FPGA通信时,FPGA端通过SRIO写入的数据放在DDR3_SRIO_fpga_0和 DDR3_SRIO_fpga_1这两段,同时DSP这边生成的数据存在DDR3_SRIO_DATA_1和DDR3_SRIO_DATA_2这两段,另外还有一些全局的比较大的数组,我直接定义在这些地址的后面DDR3_DATA,请问这样合理吗?
另外,想问一下,在编写cmd文件的时候还有什么需要注意的问题吗?
-heap 0x800
-stack 0x1000
MEMORY
{
/* Local L2, 0.5~1MB*/
BOOT_CORE1: o = 0x11800000, l = 0x000000C0
//VECTORS: o = 0x10800400 l = 0x00000400
//LL2_RW_DATA: o = 0x10800800 l = 0x0002F800
//VECTORS: o = 0x10800000 l = 0x00000400
//LL2_RW_DATA: o = 0x10800400 l = 0x0002FC00
//VECTORS: o = 0x00800000 l = 0x00000400
//LL2_RW_DATA: o = 0x10800400 l = 0x0002FC00
LL2_RW_DATA: o = 0x11800400 l = 0x0002FC00
//VECTORS: o = 0x10810000 l = 0x00000400
//LL2_RW_DATA: o = 0x10810400 l = 0x0001FC00
/* External DDR3, upto 2GB per core */
DDR_fifo: o = 0x80000000 l = 0x01000000 /*set memory protection attribitue as execution only*/
DDR3_R_DATA: o = 0x81000000 l = 0x01000000 /*set memory protection attribitue as read only*/
DDR3_RW_DATA: o = 0x82000000 l = 0x06000000 /*set memory protection attribitue as read/write*/
DDR3_SRIO_DATA_1: o = 0x90000000 l = 0x00001F40 /*ToFPGA,8000字节*/
DDR3_SRIO_DATA_2: o = 0x90001F40 l = 0x00001F40 /*ToFPGA,8000字节*/
DDR3_SRIO_fpga_0: o = 0x90832000 l = 0x00001F40//FromFPGA,
DDR3_SRIO_fpga_1: o = 0x90833F40 l = 0x00001F40//FromFPGA,透传过来的数据
DDR3_DATA: o = 0x90835E80 l = 0x00001F40//存储本地全局数据
//DDR3_SRIO_fpga_1: o = 0x90832000 l = 0x00041000//FromFPGA可做数据读写操作的DDR空间
//DDR_fifo: o = 0x90000000 l = 0x00001000//fifo
}
SECTIONS
{
//vecs > VECTORS
.text > LL2_RW_DATA
.cinit > LL2_RW_DATA
.const > LL2_RW_DATA
.switch > LL2_RW_DATA
//.DDRText{MulticoreBoot.obj(.text)} > LL2_RW_DATA
.stack > LL2_RW_DATA
GROUP
{
.neardata
.rodata
.bss
} > LL2_RW_DATA
.far > LL2_RW_DATA
.fardata > LL2_RW_DATA
.cio > LL2_RW_DATA
.sysmem > LL2_RW_DATA
QMSS_Data.linkingRAM1 > LL2_RW_DATA
QMSS_Data.Descriptor_SL2 > LL2_RW_DATA
PacketData.buffer_SL2 > LL2_RW_DATA
PacketData.buffer_SL2 > LL2_RW_DATA
QMSS_Data.Descriptor_LL2 > LL2_RW_DATA
PacketData.buffer_LL2 > LL2_RW_DATA
PacketData.buffer_LL2 > LL2_RW_DATA
QMSS_Data.Descriptor_DDR > LL2_RW_DATA
PacketData.buffer_DDR > LL2_RW_DATA
//Verify_addr.buffer > LL2_verify_addr
//Verify_bytelen.buffer > LL2_verify_bytelen
//CORE1.buffer > DDR3_SRIO_DATA_0
//CORE1.buffer > CORE1_L2_put
.myboot
{
*.*<boot.obj>(.text)
} > BOOT_CORE1
}
Thomas Yang1:
可以这样分配的,主要需要注意不能memory不能越界,size大小要合适