想请问下,在做SPI的nor下载镜像的时候,前面的DDR3 boot table:
00 00 00 70 00 87 35 00 02 42 80 F5 00 00 00 00 00 00 00 1C 00 00 00 02
63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00
00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 03 05 这些参数是什么意思?内容可以更改吗?有什么文档是介绍这个表的呢?我随便更改一个就启动不了,但是我的DDR和开发板的DDR不一样,所以有些DDR参数是不对的。需要更改,请问应该怎么更改?
Shine:
可以参考processor sdk里的tiboot.h头文件里的
* Emif4 (DDR3) configuration table
*******************************************************************************/
typedef struct bootEmif4Tbl_s {
UINT32 configSelect; /* Bit map defining which registers to set */
UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;
UINT32 sdRamConfig;
UINT32 sdRamConfig2;
UINT32 sdRamRefreshCtl;
UINT32 sdRamTiming1;
UINT32 sdRamTiming2;
UINT32 sdRamTiming3;
UINT32 lpDdrNvmTiming;
UINT32 powerManageCtl;
UINT32 iODFTTestLogic;
UINT32 performCountCfg;
UINT32 performCountMstRegSel;
UINT32 readIdleCtl;
UINT32 sysVbusmIntEnSet;
UINT32 sdRamOutImpdedCalCfg;
UINT32 tempAlterCfg;
UINT32 ddrPhyCtl1;
UINT32 ddrPhyCtl2;
UINT32 priClassSvceMap;
UINT32 mstId2ClsSvce1Map;
UINT32 mstId2ClsSvce2Map;
UINT32 eccCtl;
UINT32 eccRange1;
UINT32 eccRange2;
UINT32 rdWrtExcThresh;
tiboot_c66x.h
user3604552:
回复 Shine:
我参考了,然后我根据这个修改了UINT32sdRamConfig;UINT32sdRamConfig2;就不行,只要变动1都不行,是不是这个数据结构有做校验?
striker Qian:
回复 user3604552:
你得到了它
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