C6678 spi boot中boot parameter table 参数 pll ，cpu频率 ，bus频率设置问题

boot parameter table 中SW PLL,CPU Freq,BUS freq 参数如何设置，在手册上没有找到，这些参数的设置是否会影响 应用程序 加载速度？

在Bootloader for KeyStone Architecture User's Guide手册中讲到在SPI模式下PLL始终处于bypass mode?

Shine：

这些参数的设置会影响加载速度。下面的帖子有回答这些参数在哪里设置。
e2e.ti.com/…/1169529

user4179460：

回复 Shine:

你好，我看了这个贴子，中间一些问题没有解释清楚，您能帮忙解释一下么？

SPI模式下 PLL工作在 bypass mode，那么 boot parameter table 中 sw pll设置是否起作用，

I understood that PLL is in bypass mode if SPI/I2C boot are used.
But I thought if setting the pll parameter in Boot parameter table,
RBL will first read this table from SPI NOR flash to internal memory(L2) and
then set the PLL controller to the expected value.
So, is this understanding wrong? Then why there are pll parameter in Boot parameter table?

Do you mean that PLL is in bypass mode and RBL won't change if SPI boot is used,
but RBL will change SPI bus frequency to expected speed?

In C6670EVM input clock is 122.88MHz, so that CorePac0 is running at 122.88MHz(bypassed)
and SPI module clock are 20.48MHz. So, is 20.48MHz the maximum SPI bus frequency in EVM SPI boot mode?