TI中文支持网如题。
目前正在调试基于BeagleBone AM335X 公司画的板子，利用了RGMII的第二路网口。
使用的PHY芯片是AT8031 两个，分别连接到 AM335X 的 RGMII1 和 RGMII2。
目前 RGMII1 对应的 eth0 是通的，工作正常。RGMII2 对应的eth1始终无法调通。
根据TI官网的 CPSW Ethernet Dual EMac 配置正确的 DeviceTree（pinmux & dual_emac = <1>，见底部），打开了 VLAN 选项。
确定了cpsw.c 中 ALE_Control 寄存器地址的 ale_vlan_aware 位设置了。
详细情况：
现象1 ： eth1 和我的电脑直连，从eth1ping通我的电脑，并用wireshark抓到了ping的请求和反馈。可反过来电脑ping eth1不通。PS.电脑百兆网口
现象2：强制使用ethtool设置网口工作模式为 100M ,autoneg off , fule duplex模式，通过eth1 无法ping通外界。
现象3：设置eth1 的IP地址，外界能够ping通eth1的IP，但是从 eth0 进入的！！！看上去eth0模拟了虚拟IP。
原理理解：
CPSW 仅仅只是一个MAC来管理两个 PHY，所以中间引入了一个 ALE(address lookup engine)来做片选哪个PHY的工作。这样来管理两个PHY，并正常工作。不确定我理解的对不，所以查阅了 ALE_Control 和 ale_vlan_aware 寄存器均正确。
参考1 ， device tree 节选：
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
/*0x110 (PIN_INPUT_PULLUP | MUX_MODE2)*/ /* rgmii1_rxerr.rgmii1_rxerr */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* rgmii1_txen.rgmii1_txen */
0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* rgmii1_rxdv.rgmii1_rxdv */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* rgmii1_txd3.rgmii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* rgmii1_txd2.rgmii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* rgmii1_txd1.rgmii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* rgmii1_txd0.rgmii1_txd0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* rgmii1_txclk.rgmii1_txclk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* rgmii1_rxclk.rgmii1_rxclk */
0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* rgmii1_rxd3.rgmii1_rxd3 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* rgmii1_rxd2.rgmii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* rgmii1_rxd1.rgmii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* rgmii1_rxd0.rgmii1_rxd0 */
/* Slave 2 */
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
>;
};
……
……
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
mac-address = [ 12 23 34 45 56 67 ];
phy-mode = "rgmii";
dual_emac_res_vlan = <0>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii";
mac-address = [ 22 32 43 54 65 76 ];
dual_emac_res_vlan = <0>;
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac;
};
参考2, Dual Emac 配置方法，节选 AM335X Technical Reference:
14.3.2.10.2 Dual Mac Mode
When operating in dual mac mode the intention is to transfer packets between ports 0 and 1 and ports 0
and 2, but not between ports 1 and 2. Each CPGMAC_SL appears as a single MAC with no bridging
between MAC’s. Each CPGMAC_SL has at least one unique (not the same) mac address.
Dual mac mode is configured as described below:
• Set the ale_vlan_aware bit in the ALE_Control register. This bit configures the ALE to process in vlan
aware mode.The CPSW_3G vlan aware bit (vlan_aware in CPSW_Control) determines how packets
VLAN’s are processed on CPGMAC_SL egress and does not affect how the ALE processes packets or
the packet destination. The CPSW_3G vlan aware bit may be set or not as required (must be set if
VLAN’s are to exit the switch).
• Configure the Port 1 to Port 0 VLAN
Add a VLAN Table Entry with ports 0 and 1 as members (clear the flood masks).
Add a VLAN/Unicast Address Table Entry with the Port1/0 VLAN and a port number of 0. Packets
received on port 1 with this unicast address will be sent only to port 0 (egress). If multiple mac addresses
are desired for this port then multiple entries of this type may be configured.
• Configure the Port 2 to Port 0 VLAN
Add a VLAN Table Entry with ports 0 and 2 as members (clear the flood masks).
Add a VLAN/Unicast Address Table Entry with the Port2/0 VLAN and a port number of 0. Packets
received on port 2 with this unicast address will be sent only to port 0 (egress). If multiple mac addresses
are desired for this port then multiple entries of this type may be configured.
• Packets from the host (port 0) to ports 1 and 2 should be directed. If directed packets are not desired
then VLAN with addresses can be added for both destination ports.
• Select the dual mac mode on the port 0 FIFO by setting tx_in_sel[1:0] = 01 in P0_Tx_In_Ctl. The
intention of this mode is to allow packets from both ethernet ports to be written into the FIFO without
one port starving the other port.
• The priority levels may be configured such that packets received on port 1 egress on one CPDMA RX
channel while packets received on port 2 egress on a different CPDMA RX channel.
PS. 我照做了，也确认过没有问题。
参考3， TI 官网 CPSW Ethernet配置介绍：
http://processors.wiki.ti.com/index.php/AM335x_CPSW_(Ethernet)_Driver%27s_Guide#Dual_Standalone_EMAC_mode
我照做了，其中使用的SDK比较老，基于 kernel v3.2 的，而最新的基于 kernel v3.12 是 sdk7.0，但是发现最后的并没有这个选项： Emac switch 。有其他建议么？
期待回复啊。有人有类似的经验么？AM335X 第二路网口调通过的同仁们。
Yaoming Qin：
am33xx_cpsw_init 后面的两个参数，应该是phy本身的地址，写成字符串的形式。
这个加了吗
philip pi：
回复 Yaoming Qin:
具体能说明在哪个源文件么？我看其他帖子也经常提到这个接口。但我貌似没有找到对一个的地方，麻烦提示下，谢谢。
Yaoming Qin：
回复 philip pi:
请查看 arch/arm/mach-omap2/board-am335xevm.c
philip pi：
回复 Yaoming Qin:
我目前使用的Linux版本是 3.14 ，我grep 了一下 所有am33xx_cp开头的，只能找到这些。
[philip@catonbj arm]$ grep -rn "am33xx_cp"Binary file mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.o matchesBinary file mach-omap2/omap_hwmod_43xx_data.o matchesBinary file mach-omap2/omap_hwmod_33xx_data.o matchesmach-omap2/omap_hwmod_43xx_data.c:484: .slave = &am33xx_cpgmac0_hwmod,mach-omap2/omap_hwmod_43xx_data.c:743: &am33xx_cpgmac0__mdio,Binary file mach-omap2/built-in.o matchesmach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c:149:struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c:150: .master = &am33xx_cpgmac0_hwmod,mach-omap2/omap_hwmod_33xx_43xx_common_data.h:36:extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;mach-omap2/omap_hwmod_33xx_43xx_common_data.h:95:extern struct omap_hwmod am33xx_cpgmac0_hwmod;Binary file mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.o matchesmach-omap2/omap_hwmod_33xx_data.c:464: .slave = &am33xx_cpgmac0_hwmod,mach-omap2/omap_hwmod_33xx_data.c:631: &am33xx_cpgmac0__mdio,mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:316:static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:327:static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:329: .sysc = &am33xx_cpgmac_sysc,mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:332:struct omap_hwmod am33xx_cpgmac0_hwmod = {mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:334: .class = &am33xx_cpgmac0_hwmod_class,mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:1376: CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:1449: CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
是否后续的Linux版本已经对整个框架有一些调整？
Yaoming Qin：
回复 philip pi:
您用的是ezsdk 7.0么
那么应该修改下您的板子对应的dts文件， 可以参考 am335x-evmsk.dts 中的cpsw_emac1等的配置。
Jian Zhou：
回复 Yaoming Qin:
可以先在u-boot下把第二个网口测一下，排除下硬件的嫌疑
philip pi：
回复 Yaoming Qin:
Hi,Yaoming Qin:
我后来使用了 EZSDK7.0 之后（Linux 3.12），基于BB板，所以根据 am335x-evmsk.dts 配置的 am335x-bone-common.dtsi 对应网口的部分：
cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
/* Slave 2 */ 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; };
cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 reset value*/ 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) >; };
…
&mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; dual_emac;};
&davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>;};
&cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rgmii";};
&cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii";};
…
现象：
eth0 eth1 均有，ifconfig eth1 up并配置好IP（ETH0 ETH1同网段）之后，从第二个网口并不能ping通，但把eth0网口插上，两个IP均可ping通，第二个网口可有可无。两个IP的数据均从ETH0进出。ETH0 和 ETH1 配置不同网段的IP，则无法访问 ETH1 的IP了。
值得一提的是,拔插两个网线都有如下打印：
eth0
[ 1632.098610] libphy: 4a101000.mdio:00 – Link is Up – 100/Full
eth1
[ 1632.098610] libphy: 4a101000.mdio:01 – Link is Up – 100/Full
硬件上的图片如图，两块8031的网口芯片，分别对应两个网口，左边是ETH1，右边是ETH0.
philip pi：
回复 Jian Zhou:
在Uboot中做过如下实验：
在boardinit的地方，cpsw有两个slave,默认使用第一个网口，后把顺序交换了一下，从第二个网口能够ping通外面。硬件上参考evm板做的，应该问题不大。可能在软件/dts的配置上。
Bernie Chen：
回复 philip pi:
我 eth1 無法 ping 通卡了3個月了，這問題還是沒解。只要是 sdk7以上，都是這樣….官方給我的解答是大部分客戶用的是sdk6，sdk8少人碰。
關於dts，我在E2E有人 AR8035 可以通，只是沒問她的 phy 是在slave1 還是 slave 2，然後dts也只是跟我說 phi_id 修改 & phy mode 修改就好了。
可我的還是不行，ˋ這位大俠有甚麼心得題示能給小弟我嗎? 感激不盡
Miao Tian1：
回复 philip pi:
请问您后来的问题解决了吗？
