F28377D IPC如何产生中断

在cpu2配置ipc0-3中断后，在cpu1设置IpcRegs.IPCSET.bit.IPC0 = 1;后，为什么cpu2上相应的PIE中断标志并未被置位？IPC中的4个中断是如何产生的？

cpu2上中断配置如下：

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.IPC0_INT = &IPC0_ISR;
PieVectTable.IPC1_INT = &IPC1_ISR;
PieVectTable.IPC2_INT = &IPC2_ISR;
PieVectTable.IPC3_INT = &IPC3_ISR;
EDIS; // This is needed to disable write to EALLOW protected registers

IER |= M_INT1;

PieCtrlRegs.PIEIER1.bit.INTx13 = 1;
PieCtrlRegs.PIEIER1.bit.INTx14 = 1;
PieCtrlRegs.PIEIER1.bit.INTx15 = 1;
PieCtrlRegs.PIEIER1.bit.INTx16 = 1;

InitIpc();

EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

Eric Ma：

参考一下这个例程：

C:\ti\controlSUITE\device_support\f28m35x\v208\F28M35x_examples_Dual\ctom_ipcdrivers

初始化IPC后，在置为IPC后，你先查看一下CPU1上的IPC标志位有没置1.

IER |= M_INT1;  这里应该错了。是M_INT11.

ERIC

在cpu2配置ipc0-3中断后，在cpu1设置IpcRegs.IPCSET.bit.IPC0 = 1;后，为什么cpu2上相应的PIE中断标志并未被置位？IPC中的4个中断是如何产生的？

cpu2上中断配置如下：

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.IPC0_INT = &IPC0_ISR;
PieVectTable.IPC1_INT = &IPC1_ISR;
PieVectTable.IPC2_INT = &IPC2_ISR;
PieVectTable.IPC3_INT = &IPC3_ISR;
EDIS; // This is needed to disable write to EALLOW protected registers

IER |= M_INT1;

PieCtrlRegs.PIEIER1.bit.INTx13 = 1;
PieCtrlRegs.PIEIER1.bit.INTx14 = 1;
PieCtrlRegs.PIEIER1.bit.INTx15 = 1;
PieCtrlRegs.PIEIER1.bit.INTx16 = 1;

InitIpc();

EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

sijie hu：

回复 Eric Ma:

在置位IPC相应位后，对应的标志位也被置位，同时另一个cpu状态为也被置位，

唯独PIE中的中断标志位没有被置位，在PIE寄存器中对应的PIEIER位已经使能，为何在IPC置位后，另一个cpu的PIE模块的中断标志位没有置位，

按理说只要是cpu1中IPC0-3位在IPCSET设置后，cpu2PIE模块中的中断标志应该被置位。

ipc中断在中断表中的第一组，我把IER |= M_INT1改为IER |=0xffff后仍没有变化，请指点一二。

在cpu2配置ipc0-3中断后，在cpu1设置IpcRegs.IPCSET.bit.IPC0 = 1;后，为什么cpu2上相应的PIE中断标志并未被置位？IPC中的4个中断是如何产生的？

cpu2上中断配置如下：

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.IPC0_INT = &IPC0_ISR;
PieVectTable.IPC1_INT = &IPC1_ISR;
PieVectTable.IPC2_INT = &IPC2_ISR;
PieVectTable.IPC3_INT = &IPC3_ISR;
EDIS; // This is needed to disable write to EALLOW protected registers

IER |= M_INT1;

PieCtrlRegs.PIEIER1.bit.INTx13 = 1;
PieCtrlRegs.PIEIER1.bit.INTx14 = 1;
PieCtrlRegs.PIEIER1.bit.INTx15 = 1;
PieCtrlRegs.PIEIER1.bit.INTx16 = 1;

InitIpc();

EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

Sunrise：

回复 Eric Ma:

你好，

         TI官方并没有给28377D  IPC中断的例子，哪里可以找到，谢谢！

在cpu2配置ipc0-3中断后，在cpu1设置IpcRegs.IPCSET.bit.IPC0 = 1;后，为什么cpu2上相应的PIE中断标志并未被置位？IPC中的4个中断是如何产生的？

cpu2上中断配置如下：

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.IPC0_INT = &IPC0_ISR;
PieVectTable.IPC1_INT = &IPC1_ISR;
PieVectTable.IPC2_INT = &IPC2_ISR;
PieVectTable.IPC3_INT = &IPC3_ISR;
EDIS; // This is needed to disable write to EALLOW protected registers

IER |= M_INT1;

PieCtrlRegs.PIEIER1.bit.INTx13 = 1;
PieCtrlRegs.PIEIER1.bit.INTx14 = 1;
PieCtrlRegs.PIEIER1.bit.INTx15 = 1;
PieCtrlRegs.PIEIER1.bit.INTx16 = 1;

InitIpc();

EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

Charles Ji：

回复 sijie hu:

您好，我遇上了同样的问题，cpu2 给 cpu1 发ipc0 事件，可以触发cpu1的里中断，而cpu1给cpu2发ipc事件，cpu2 没有响应，我和你配置的一样，请问后来解决了吗？