3.1 Debug Mode
Debug mode is entered by forcing two falling-edge transitions on pin P2.2 (debug clock) while the RESET_N input is held low. When RESET_N is set high, the device is in debug mode.
On entering debug mode, the CPU is in the halted state with the program counter reset to address 0x0000.
While in debug mode, pin P2.1 is the debug-data bidirectional pin, and P2.2 is the debug-clock input pin