F28069 can通信问题-TI中文支持网

F2806*例程back2back 适用的时钟频率是80Mhz这样can通信速率是1Mhz，但是F28069的时钟频率是90Mhz，需要怎么样才能更改使其传输速率为1M？附上代码，求大神们纠错

//###########################################################################
//
// FILE: F2806x_ECan.c
//
// TITLE: F2806x Enhanced CAN Initialization & Support Functions.
//
//###########################################################################
// $TI Release: F2806x C/C++ Header Files and Peripheral Examples V150 $
// $Release Date: June 16, 2015 $
// $Copyright: Copyright (C) 2011-2015 Texas Instruments Incorporated –
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

#include "F2806x_Device.h" // F2806x Headerfile Include File
#include "F2806x_Examples.h" // F2806x Examples Include File

//—————————————————————————
// InitECan:
//—————————————————————————
// This function initializes the eCAN module to a known state.
//
#if DSP28_ECANA
void InitECan(void)
{
InitECana();
}
#endif

#if DSP28_ECANA
void InitECana(void) // Initialize eCAN-A module
{

/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. */

struct ECAN_REGS ECanaShadow;

EALLOW; // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for HECC mode – (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature

ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.

ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */

ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */

ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/

ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..

ECanaShadow.CANBTC.all = 0;
/* The following block is for 80 MHz SYSCLKOUT. (40 MHz CAN module clock Bit rate = 1 Mbps
See Note at end of file. */

ECanaShadow.CANBTC.bit.BRPREG = 2;
ECanaShadow.CANBTC.bit.TSEG2REG = 3;
ECanaShadow.CANBTC.bit.TSEG1REG = 9;

ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..

/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs

EDIS;
}
#endif // endif DSP28_ECANA

//—————————————————————————
// Example: InitECanGpio:
//—————————————————————————
// This function initializes GPIO pins to function as eCAN pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for CANTXA operation.
// Only one GPIO pin shoudl be enabled for CANRXA operation.
// Comment out other unwanted lines.

#if DSP28_ECANA
void InitECanGpio(void)
{
InitECanaGpio();
}
#endif

#if DSP28_ECANA
void InitECanaGpio(void)
{
EALLOW;

/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.

GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)

/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation

EDIS;
}
#endif // endif DSP28_ECANA

/* Note: Bit timing parameters must be chosen based on the network parameters such as
the sampling point desired and the propagation delay of the network. The propagation
delay is a function of length of the cable, delay introduced by the
transceivers and opto/galvanic-isolators (if any).

The parameters used in this file must be changed taking into account the above mentioned
factors in order to arrive at the bit-timing parameters suitable for a network.
*/

//===========================================================================
// End of file.
//===========================================================================

user4669117：

主程序如下：

//###########################################################################// Description//! \addtogroup f2833x_example_list//! <h1>eCAN-A to eCAN-B Trasmit Loop (ecan_a_to_b_xmit)</h1>//!//! This example TRANSMITS data to another CAN module using MAILBOX5//! This program could either loop forever or transmit "n" # of times,//! where "n" is the TXCOUNT value. \n//!//! This example can be used to check CAN-A and CAN-B. Since CAN-B is//! initialized in DSP2833x_ECan.c, it will acknowledge all frames//! transmitted by the node on which this code runs. Both CAN ports of//! the 2833x DSP need to be connected to each other (via CAN transceivers)//!//! \b External \b Connections \n//! – eCANA is on GPIO31 (CANTXA) and GPIO30 (CANRXA)//! – eCANB is on GPIO8 (CANTXB) and GPIO10 (CANRXB)//! – Connect eCANA to eCANB via CAN transceivers////###########################################################################// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $// $Release Date: November 1, 2016 $// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -// http://www.ti.com/ ALL RIGHTS RESERVED $//###########################################################################

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File

#define TXCOUNT 100 // Transmission will take place (TXCOUNT) times..

// Globals for this examplelong i;long loopcount = 0;void delay_ms(unsigned int t);void main(){// Create a shadow register structure for the CAN control registers. This is// needed, since only 32-bit access is allowed to these registers. 16-bit access// to these registers could potentially corrupt the register contents or return// false data.

struct ECAN_REGS ECanaShadow;

// Step 1. Initialize System Control:// PLL, WatchDog, enable Peripheral Clocks// This example function is found in the DSP2833x_SysCtrl.c file. InitSysCtrl();

// Step 2. Initialize GPIO:// This example function is found in the DSP2833x_Gpio.c file and// illustrates how to set the GPIO to it's default state.// InitGpio(); // Skipped for this example

// Just initialize eCAN pins for this example// This function is in DSP2833x_ECan.c InitECanGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:// Disable CPU interrupts DINT;

// Initialize the PIE control registers to their default state.// The default state is all PIE interrupts disabled and flags// are cleared.// This function is found in the DSP2833x_PieCtrl.c file. InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt// Service Routines (ISR).// This will populate the entire table, even if the interrupt// is not used in this example. This is useful for debug purposes.// The shell ISR routines are found in DSP2833x_DefaultIsr.c.// This function is found in DSP2833x_PieVect.c. InitPieVectTable();

// Interrupts that are used in this example are re-mapped to// ISR functions found within this file.

// No interrupts used in this example.

// Step 4. Initialize all the Device Peripherals:// This function is found in DSP2833x_InitPeripherals.c// InitPeripherals(); // Not required for this example

// In this case just initialize eCAN-A and eCAN-B// This function is in DSP2833x_ECan.c InitECan();

// Step 5. User specific code:

/* Write to the MSGID field */ //设置接收邮箱 //设置接收邮箱的ID，扩展帧 ECanaShadow.CANME.all = ECanaRegs.CANME.all; ECanaRegs.CANME.bit.ME16= 0; ECanaMboxes.MBOX16.MSGID.all = 0x80C20000;//邮箱ID？？？怎么设置

//设置邮箱16为接收邮箱 ECanaShadow.CANMD.all = ECanaRegs.CANMD.all; ECanaShadow.CANMD.bit.MD16 =1; ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

//数据长度 8个BYTE ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8;

//没有远方应答帧被请求*/ ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0;

//邮箱使能 ECanaShadow.CANME.all = ECanaRegs.CANME.all; ECanaShadow.CANME.bit.ME16 =1; ECanaRegs.CANME.all = ECanaShadow.CANME.all;

//邮箱中断使能 EALLOW; ECanaRegs.CANMIM.all = 0xFFFFFFFF; //邮箱中断将产生在ECAN0INT ECanaRegs.CANMIL.all = 0; ECanaRegs.CANGIF0.all = 0xFFFFFFFF; //ECAN0INT中断请求线被使能 ECanaRegs.CANGIM.bit.I0EN = 1; EDIS; //使能PIE中断 PieCtrlRegs.PIEIER9.bit.INTx5 = 1;

//使能CPU中断 IER |= M_INT9;

EINT; //开全局中断 ERTM; //开实时中断//设置can_ID ECanaMboxes.MBOX25.MSGID.all = 0x110; // Extended Identifier，做标准帧，不做为扩展帧了

/* Configure Mailbox under test as a Transmit mailbox */

ECanaShadow.CANMD.all = ECanaRegs.CANMD.all; ECanaShadow.CANMD.bit.MD25 = 0; ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox under test */

ECanaShadow.CANME.all = ECanaRegs.CANME.all; ECanaShadow.CANME.bit.ME25 = 1; ECanaRegs.CANME.all = ECanaShadow.CANME.all; delay_ms(500);

//对1组驱动器进行复位

/* Write to DLC field in Master Control reg */

ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8; //设置数据长度的字节数//

/* Write to the mailbox RAM field */

ECanaMboxes.MBOX25.MDL.all = 0x55555555; //往发送邮箱中写数据，分别写低32位4字节和高32位4字节 ECanaMboxes.MBOX25.MDH.all = 0x55555555;

/* Begin transmitting */ //置位准备发送，将发送请求位置位，使能邮箱发送功能

for(i=0; i < TXCOUNT; i++) { ECanaShadow.CANTRS.all = 0; ECanaShadow.CANTRS.bit.TRS25 = 1; // Set TRS for mailbox under test ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

do { ECanaShadow.CANTA.all = ECanaRegs.CANTA.all; } while(ECanaShadow.CANTA.bit.TA25 == 0 ); // Wait for TA5 bit to be set..

ECanaShadow.CANTA.all = 0; ECanaShadow.CANTA.bit.TA25 = 1; // Clear TA5 ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

loopcount ++; }

delay_ms(500); //设置can_ID ECanaMboxes.MBOX25.MSGID.all = 0x111; // Extended Identifier，做标准帧，不做为扩展帧了 /* Write to the mailbox RAM field */

ECanaMboxes.MBOX25.MDL.all = 0x55555555; //往发送邮箱中写数据，分别写低32位4字节和高32位4字节 ECanaMboxes.MBOX25.MDH.all = 0x55555501;

/* Begin transmitting */ //置位准备发送，将发送请求位置位，使能邮箱发送功能

for(i=0; i < TXCOUNT; i++) { ECanaShadow.CANTRS.all = 0; ECanaShadow.CANTRS.bit.TRS25 = 1; // Set TRS for mailbox under test ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

do { ECanaShadow.CANTA.all = ECanaRegs.CANTA.all; } while(ECanaShadow.CANTA.bit.TA25 == 0 ); // Wait for TA5 bit to be set..

ECanaShadow.CANTA.all = 0; ECanaShadow.CANTA.bit.TA25 = 1; // Clear TA5 ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

loopcount ++; }

delay_ms(500); ECanaMboxes.MBOX25.MSGID.all = 0x112; // Extended Identifier，做标准帧，不做为扩展帧了 /* Write to the mailbox RAM field */

ECanaMboxes.MBOX25.MDL.all = 0x55555555; //往发送邮箱中写数据，分别写低32位4字节和高32位4字节 ECanaMboxes.MBOX25.MDH.all = 0x5555080D;

/* Begin transmitting */ //置位准备发送，将发送请求位置位，使能邮箱发送功能

for(i=0; i < TXCOUNT; i++) { ECanaShadow.CANTRS.all = 0; ECanaShadow.CANTRS.bit.TRS25 = 1; // Set TRS for mailbox under test ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

do { ECanaShadow.CANTA.all = ECanaRegs.CANTA.all; } while(ECanaShadow.CANTA.bit.TA25 == 0 ); // Wait for TA5 bit to be set..

ECanaShadow.CANTA.all = 0; ECanaShadow.CANTA.bit.TA25 = 1; // Clear TA5 ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

loopcount ++; }

__asm(" ESTOP0"); // Stop here}

//延时函数void delay_ms(unsigned int t){ unsigned int i; for( i=0;i<t;i++) { unsigned int a=37500; //at 168MHz 42000 is ok while(a–); }}

void delay_us(unsigned int t){ unsigned int i; for( i=0;i<t;i++) { unsigned int a=38; //at 168MHz 40 is ok,the higher the number the more timing precise while(a–); }}

#include "F2806x_Device.h" // F2806x Headerfile Include File
#include "F2806x_Examples.h" // F2806x Examples Include File

#if DSP28_ECANA
void InitECana(void) // Initialize eCAN-A module
{

struct ECAN_REGS ECanaShadow;

EALLOW; // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for HECC mode – (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature

ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.

ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */

ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */

ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/

ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

ECanaShadow.CANBTC.all = 0;
/* The following block is for 80 MHz SYSCLKOUT. (40 MHz CAN module clock Bit rate = 1 Mbps
See Note at end of file. */

ECanaShadow.CANBTC.bit.BRPREG = 2;
ECanaShadow.CANBTC.bit.TSEG2REG = 3;
ECanaShadow.CANBTC.bit.TSEG1REG = 9;

ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs

EDIS;
}
#endif // endif DSP28_ECANA

#if DSP28_ECANA
void InitECanGpio(void)
{
InitECanaGpio();
}
#endif

#if DSP28_ECANA
void InitECanaGpio(void)
{
EALLOW;

GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.

GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)

/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation

EDIS;
}
#endif // endif DSP28_ECANA

The parameters used in this file must be changed taking into account the above mentioned
factors in order to arrive at the bit-timing parameters suitable for a network.
*/

//===========================================================================
// End of file.
//===========================================================================

Seven Han：

回复 user4669117:

您好，

请参考收据手册http://www.ti.com.cn/cn/lit/ug/spruh18g/spruh18g.pdf 16.10.2章节CAN Bit Rate Calculation。

F28069 can通信问题

相关推荐

热门标签

热门文章

QQ咨询

回顶部