TI中文支持网Part Number:DAC12DL3200
Tool/software:
Hi,
We are working on DAC12DL3200 Digital to analog converter(DAC) with LVDS Interface operating with Dual channel, 4 LVDS buses.
We setDACCLK 1G, LVDS CLK 125M, and SYSREF 10M. The STROBE is set every 8 periods of LVDS CLK, which meets the provided time sequence for MODE 0 (we use the STROBE pin).
The NCO MODE is working correctly, but the LVDS MODE has no output.
However, we read the register:
SYNC_STATUS Register(0x800) always be f0;
LVDS_ALM Register(0X821) always be ff (no matter STROBE is given or not);
FIFO_ALM Register(0x820) always be 00(we assume the data has never get in to the FIFO);
Our register config is shown below:
x"000080",–Assert reset
x"000000",–De-assert reset
x"010151", –51 LVDS
x"004800",–set DCM_EN
x"002103",–disable AUTOMUTE，TXEN pin ENABLE
x"010600",–LVDS_RESOLUTION & 1: STROBE; 0:LSB_SYNC
x"016000",–output mode
x"0823FF",–set MUTE_MASK Register
x"0824FF",–set MUTE_MASK Register
x"890000",–Read FUSE_DONE
x"010001", –SET DP_EN
x"0821FF", –CLEAR ALM
x"022002", — FIFO ALIGN x"880000",–wait for LVDS_STROBE_DET
x"020007", — config FIFO DLY
x"0822FF" — Clear ALL SYS_ALM bits
Why LVDS MODE have no output? and the ALM Register is not changing as we expected, could you plz help us out?
Taylor：
您好，
已经收到了您的案例，调查需要些时间，感谢您的耐心等待。
,
Vivian Gao：
Have you confirmed the timing on the FPGA? Also can you confirm all of the clocking is phase locked. (10MHz reference locked, etc).
