TI中文支持网Part Number:SN75LVPE3410
1、Communication between XILINX KU060 and X86 is conducted via PCIE. Due to the long layout routing, buffer(SN75LVPE3410) is adopted for enhanced driving
2、Due to the excessive length of the wiring harness, two SN75LVPE3410s were added in the middle of the link
3、the settings of the buffer are as shown in the above figure.The result is that the PCIE bandwidth is reduced from X4 to X1
I want to know if there is anything wrong with this design!
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Taylor：
您好，
已经收到了您的案例，调查需要些时间，感谢您的耐心等待。
,
meixiang dong：
Do you have any ideas?
,
Links：
Hi,
Can you list the loss of each segment FPGA -> loss(dB) -> SN75LVPE3410 -> loss(dB) -> SN75LVPE3410 -> Loss(dB) -> EP
Is this a PCIe Gen 3 application?
Does the link connect at Gen 3 x1?
Will the link connect x4 at lower speeds @ Gen 2 or Gen 1?
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