why PDMCK no signal out?

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Taylor：

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

,

Links：

Hi,

What MCLK, BCLK, and WCLK are you using? I saw you configured GPIO1 as MCLK input. Are you using the device in controller or target mode? (are you providing the BCLK and WCLK as well or just MCLK?). Also, I saw that you set all GPO1-4 as PDM clock out. You only need to set one of these as the PDM clock out. How are your PDM mics connected, can you attach a schematic? One more thing of note is that I see you have I2S mode enabled, but you have 8 channels enabled in the ASI. You should use TDM mode for this (set with register  0x07) as I2S mode is only stereo. I will attach your config with my comments.

# CHECKSUM 0
# Generated by ADCx140EVM-SW v3.0.5
# TLV320ADC3140 device configuration
# -----------------------------------------------------------------------------
# Reset
# -----------------------------------------------------------------------------
# Select Page 0
w 98 00 00
# Reset Device
w 98 01 01
# 1mS Delay
# -----------------------------------------------------------------------------
# Begin Device Memory
# -----------------------------------------------------------------------------
# Page 0 (0x00) Dump
# Select Page 0
w 98 00 00
# Wake up and enable AREG
w 98 02 81
# ASI Configuration
w 98 07 40 #i2s mode (this should be tdm mode if 8 channels are used), 16 bit
w 98 08 20w 98 09 20 #disable bus error detection?
# Clock Error Disable/Enable
w 98 04 40 #reserved register, i think
# GPIO Configuration
w 98 21 a2 #gpio1 is mclk input
# GPO Configuration
w 98 22 40 #gpo1 is pdm clock output
w 98 23 41 #gpo2 is pdm clock output?
w 98 24 41 #gpo3 is pdm clock output?
w 98 25 41 #gpo4 is pdm clock output?
# GPI Configuration
w 98 2b 45 #gpi1 is pdm data input for ch1 and ch2, gpi2 is pdm data for ch3 and ch4
w 98 2c 67 #gpi3 is pdm data for ch5 and ch6, gpi4 is pdm data for ch7 and ch8
w 98 32 04 #only unmasked interrupts canbe read with ltch
w 98 33 3f #do not mask clock and lock interrupts
# Channel 1 configuration
w 98 3c 40 #ch1 is digital mic pdm input
# Channel 2 configuration
w 98 41 40 #ch2 is dig mic pdm input
# Channel 3 configuration
w 98 46 40 #ch3 is dig mic pdm input
# Channel 4 configuration
w 98 4b 40 #ch4 dig mic pdm input
#DSP configuration
w 98 6c 28 #2 biquads per channel, soft stepping disabled
# Channel Input/Output Configuration
w 98 73 ff #ch 1-8 enabled
w 98 74 ff #asi ch1-8 is enabled
w 98 1e 82 # ????? not sure what this register is, likely reserved
# M divider Enabled with Divider Valuew 98 1f c0 #PDMCLK is 2.8224 or 3.072MHz

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English

Arabic
Hebrew
Polish

Bulgarian
Hindi
Portuguese

Catalan
Hmong Daw
Romanian

Chinese Simplified
Hungarian
Russian

Chinese Traditional
Indonesian
Slovak

Czech
Italian
Slovenian

Danish
Japanese
Spanish

Dutch
Klingon
Swedish

English
Korean
Thai

Estonian
Latvian
Turkish

Finnish
Lithuanian
Ukrainian

French
Malay
Urdu

German
Maltese
Vietnamese

Greek
Norwegian
Welsh

Haitian Creole
Persian

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