AM6442: AM6442 platform ICSSG1 port0 port1

os : RTOS
icssg dirver: porting from uboot in sdk9.0

test method: phy internal loopback

compile chain:
gcc ICSSG1 port0 and port1 work normal

clang + llvm ICSSG1 port0 and port1 sometimes can not receive data.
When powered on, if ICSSG1 port0 and port1 is working properly, the port will work properly.
When powered on, if ICSSG1 port0 and port1 cannot receive data, it cannot receive data all the time

debug method and result :

1、 dump all registers of icssg1 MII_G and CFG , Compare the value of the register under normal and abnormal conditions, the values are the same .
2、 dump the MII_G statics register under abnormal conditions , find that MII_G module have received the data , but The receive interrupt did not occur.

Alice：

您好，

   在AM64x-EVM测试了SDC-101 示例"ICSSG PHY loopback"，是可以调通的。

   

=============================Enet Loopback: Iteration 1=============================
ICSSG_DUALMAC Test
Enabling clocks!Initconfigs EnetType:1, InstId :3
----------------------------------------------
Open MAC port 2
EnetPhy_bindDriver: PHY 3: OUI:080028 Model:0f Ver:01 <-> 'DP83869' : OK
PHY 3 is alive
PHY 15 is alive
initQs() txFreePktInfoQ initialized with 16 pkts- HOST PORT statistics
--------------------------------hostTxByteCnt= 9233622852480008192hostRxByteCntSlice0= 9233544220218753024hostRxByteCntSlice1= 9233078426720534528hostTxByteCntSlice0= 9233110776414208000hostTxByteCntSlice1= 9233622852480008192Mac 1 statistics
--------------------------------Icssg_handleLinkUp: icssg1-2: Port 2: Link up: 100-Mbps Full-Duplex
completed- HOST PORT statistics
--------------------------------hostRxByteCnt= 723396131869949952hostTxByteCnt= 9233128695017766912hostRxByteCntSlice0= 720576241026990080hostRxByteCntSlice1= 9233103672538300416hostTxByteCntSlice0= 47244640256hostTxByteCntSlice1= 10252409058099200hostRxPktCntSlice1= 1000hostTxPktCntSlice1= 1000Mac 1 statistics
--------------------------------rxGoodFrames= 1000rxBCastFrames= 1000rxMCastFrames= 1000rxClass8= 1000rxClass9= 1000rxBucket5SizedFrame= 1000rxTotalByte= 518000rxTxTotalByte= 1044000txGoodFrame= 1000txBcastFrame= 1000txMcastFrame= 1000txBucket5SizedFrame= 1000txTotalByte= 526000Icssg_unregisterEventCb: icssg1-2: event not registered 1
Unregister TX timestamp callback
Icssg_unregisterEventCb: icssg1-2: event not registered 64
Disabling clocks for ENET: 1, inst:3!
Test complete: PASS
Loopback application completed
All tests have passed!!

https://www.ti.com/tool/download/MCU-PLUS-SDK-AM64X/10.01.00.32

https://www.ti.com/tool/download/SYSCONFIG/1.22.0.3893

https://www.ti.com/tool/download/ARM-CGT-CLANG/4.0.1.LTS

https://www.ti.com/tool/download/CCSTUDIO/12.8.1

   

,

zhang pengdong：

AM6442: ICSSG1 receive length is increased 1532

os : RTOSicssg dirver: porting from uboot in sdk9.0

test method: phy internal loopback

compile chain:             gcc

When testing RAW data, send 1024 bytes of data every 1ms, receive the data, and check the receive length, which can sometimes be 1532.

Read the statistics register of the MII_G module to show that the total data length received can be evenly divided by the length of each packet, that is, the length of the data received by the MII_G module is no problem.

There is a problem with the pru module receiving data and then transmitting it to DMA.

What is the cause of this problem and how can I solve it

,

Alice：

您好，

    请问您测试的是TI的SDK还是自己的代码？

zhang pengdong 说：icssg dirver: porting from uboot in sdk9.0

    这是 R5F 或 A53 上的示例？原因是不支持 A%3 上的 ICSSG。

   您遇到 GCC 或 clang 的问题？

,

chuan xing：

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1470781/am6442-am6442-platform-icssg1-port0-port1-not-work-when-use-clang-compile-chain  问题已迁移到此，并且已解决。谢谢！