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TLV320ADC5140: TLV320ADC5140 Unable to capture sound

2025-02-18 分类：音频 阅读(206)

Part Number:TLV320ADC5140

I'm currently using an STM32F407ZGT6 to control a TLV320ADC5140 using SPI communication to receive audio using I2S, but I'm unable to capture the audio data. Acquisition method: analog dual channel input。

STM32 as host ADC as slave。

Here is my register configuration

adc_write_reg(ADCX140_PAGE_SELECT,0x00);
adc_write_reg(ADCX140_SW_RESET,0x00);
adc_write_reg(ADCX140_SLEEP_CFG,0x00);
adc_write_reg(ADCX140_SHDN_CFG,0x05);
adc_write_reg(ADCX140_ASI_CFG0,0x40);
adc_write_reg(ADCX140_ASI_CFG1,0x00);
adc_write_reg(ADCX140_ASI_CFG2,0x00);
adc_write_reg(ADCX140_ASI_CH1,0x00);
adc_write_reg(ADCX140_ASI_CH2,0x01);
adc_write_reg(ADCX140_ASI_CH3,0x02);
adc_write_reg(ADCX140_ASI_CH4,0x03);
adc_write_reg(ADCX140_ASI_CH5,0x04);
adc_write_reg(ADCX140_ASI_CH6,0x05);
adc_write_reg(ADCX140_ASI_CH7,0x06);
adc_write_reg(ADCX140_ASI_CH8,0x07);
adc_write_reg(ADCX140_MST_CFG0,0x02);
adc_write_reg(ADCX140_MST_CFG1,0x48);
adc_write_reg(ADCX140_ASI_STS,0xff);
adc_write_reg(ADCX140_CLK_SRC,0x10);
adc_write_reg(ADCX140_PDMCLK_CFG,0x40);
adc_write_reg(ADCX140_PDM_CFG,0x00);
adc_write_reg(ADCX140_GPIO_CFG0,0xb1),
adc_write_reg(ADCX140_GPO_CFG0,0x00);
adc_write_reg(ADCX140_GPO_CFG1,0x00);
adc_write_reg(ADCX140_GPO_CFG2,0x00);
adc_write_reg(ADCX140_GPO_CFG3,0x00);
adc_write_reg(ADCX140_GPO_VAL,0x00);
adc_write_reg(ADCX140_GPIO_MON,0x00);
adc_write_reg(ADCX140_GPI_CFG0,0x00);
adc_write_reg(ADCX140_GPI_CFG1,0x20); //2d = GPI3 is configured as a master clock input (MCLK)
adc_write_reg(ADCX140_GPI_MON,0x00);
adc_write_reg(ADCX140_INT_CFG,0x00);
adc_write_reg(ADCX140_INT_MASK0,0xff);
adc_write_reg(ADCX140_INT_LTCH0,0x00);
adc_write_reg(ADCX140_BIAS_CFG,0x00);
adc_write_reg(ADCX140_CH1_CFG0,0x20);
adc_write_reg(ADCX140_CH1_CFG1,0x00);
adc_write_reg(ADCX140_CH1_CFG2,0xc9);
adc_write_reg(ADCX140_CH1_CFG3,0x80);
adc_write_reg(ADCX140_CH1_CFG4,0x00);
adc_write_reg(ADCX140_CH2_CFG0,0x20);
adc_write_reg(ADCX140_CH2_CFG1,0x00);
adc_write_reg(ADCX140_CH2_CFG2,0xc9);
adc_write_reg(ADCX140_CH2_CFG3,0x80);
adc_write_reg(ADCX140_CH2_CFG4,0x00);

adc_write_reg(ADCX140_DSP_CFG0,0x01);
adc_write_reg(ADCX140_DSP_CFG1,0x40);
adc_write_reg(ADCX140_DRE_CFG0,0x7b);
adc_write_reg(ADCX140_AGC_CFG0,0xe7);
adc_write_reg(ADCX140_IN_CH_EN,0x80);
adc_write_reg(ADCX140_ASI_OUT_CH_EN,0x80);
adc_write_reg(ADCX140_PWR_CFG,0xf4);
adc_write_reg(ADCX140_DEV_STS0,0x80);
adc_write_reg(ADCX140_DEV_STS1,0x80);
adc_read_reg(ADCX140_IN_CH_EN,0x80);
adc_read_reg(ADCX140_ASI_OUT_CH_EN,0x80);

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Links：

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待

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? ?：

非常感谢，期待您的答复

,

Links：

Hi,

The "ADCX140_SLEEP_CFG" needs to be set to 0x81 or 0x01 depending on AVDD conditions, if kept in 0x00 device will remain in sleep mode.

Additionally, the ADCX140_DEV_STS0/ADCX140_DEV_STS1 registers are read only registers, and hence cannot be written into.

Thanks and Regards,

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? ?：

 Thanks for the reply, I reworked the register but still can't hear the sound！！!

       // ADC5140寄存器配置

              adc_PAGE(0x00);                                                                       /*选择寄存器的页码*/

              ADC_DATE_INPUT(0x02 , 0x81);                                         /*上电*/

              ADC_DATE_INPUT(0x05 , 0x3C);            /*配置设备关机*/

              ADC_DATE_INPUT(0x07 , 0x40);            /*ASI_CFG0 Registery音频输出配置*/

              ADC_DATE_INPUT(0x08 , 0x60);            /*ASI_CFG1 Registery音频输出配置*/

              ADC_DATE_INPUT(0x09 , 0x00);            /*ASI_CFG2 Registery音频输出配置*/

              ADC_DATE_INPUT(0x0B , 0x00);            /*ASI_CH1 Registery音频输出配置*/

             

//            ADC_DATE_INPUT(0x13 , 0x81);            /*设备配置为 主模式，并且时钟信号（BCLK 和 FSYNC）由外部 MCU 生成*/

              ADC_DATE_INPUT(0x13 , 0x11);            /*设备配置为 从模式，并且时钟信号（BCLK 和 FSYNC）由外部 MCU 生成*/

              adc_write_reg(0x14, 0x42);                        /* 配置采样率，48KHZ */

              ADC_DATE_INPUT(0x15 , 0x42);          /*该寄存器是 ASI 总线时钟监控状态寄存器。*/ 

              ADC_DATE_INPUT(0x16 , 0x88);                       /*MCLK（GPIO 或 GPIx）用作音频根时钟源（MCLK 与 FSYNC 的比率根据 MCLK_RATIO_SEL 设置而定）*/

              ADC_DATE_INPUT(0x1F , 0x01);                               /*该寄存器是 PDM 时钟生成配置寄存器。*/

              ADC_DATE_INPUT(0x20 , 0xA0);                              /*该寄存器是 PDM DINx 采样边缘配置寄存器。*/

      

              ADC_DATE_INPUT(0x21 , 0x00);                             /*禁用输入端GPIO功能*/

              ADC_DATE_INPUT(0x22 , 0x00);                          /*禁用输入端GPI/O功能*/

              ADC_DATE_INPUT(0x23 , 0x00);              /*禁用输入端GPI/O功能*/

              ADC_DATE_INPUT(0x24 , 0x00);              /*禁用输入端GPI/O功能*/

              ADC_DATE_INPUT(0x25 , 0x00);              /*禁用输入端GPI/O功能*/

              ADC_DATE_INPUT(0x2B , 0x00);              /*禁用输入端GPI/O功能*/

              ADC_DATE_INPUT(0x2C , 0x00);              /*禁用输入端GPI/O功能*/

              ADC_DATE_INPUT(0x3B , 0x60);                                                                       /*VREF is set to 2.75 V，麦克风偏置为3.3*/

              adc_CHx_CFGx(CH1_CFG0,0xF4);

              adc_CHx_CFGx(CH1_CFG1,0xF0);

              adc_CHx_CFGx(CH1_CFG2,0xC9);

              adc_CHx_CFGx(CH1_CFG3,0x80);           

              adc_CHx_CFGx(CH1_CFG4,0x0F);

             

              adc_CHx_CFGx(CH2_CFG0,0xF4);

              adc_CHx_CFGx(CH2_CFG1,0xF0);

              adc_CHx_CFGx(CH2_CFG2,0xC9);

              adc_CHx_CFGx(CH2_CFG3,0x80);           

              adc_CHx_CFGx(CH2_CFG4,0x0F);

             

              adc_CHx_CFGx(CH3_CFG0,0xF4);

              adc_CHx_CFGx(CH3_CFG1,0xF0);

              adc_CHx_CFGx(CH3_CFG2,0xC9);

              adc_CHx_CFGx(CH3_CFG3,0x80);            

              adc_CHx_CFGx(CH3_CFG4,0x0F);

             

              adc_CHx_CFGx(CH4_CFG0,0xF4);

              adc_CHx_CFGx(CH4_CFG1,0xF0);

              adc_CHx_CFGx(CH4_CFG2,0xC9);

              adc_CHx_CFGx(CH4_CFG3,0x80);           

              adc_CHx_CFGx(CH4_CFG4,0x0F);

             

//     adc_write_reg(0x13, 0x02);          // MST_CFG0 Register

              adc_write_reg(0x73, 0xF0);          // IN_CH_EN寄存器

              adc_write_reg(0x74, 0xF0);          // ASI_OUT_CH_EN Register

              adc_write_reg(0x75, 0xF4);          // PWR_CFG Register

                    

,

Links：

Hi,

Couple of things from the configuration:

1) The SHDNZ_CFG (P0R05 has one of the fields written to a reserved value – per the script, this register is written to 0x3C)

2) Is the device expected to operate in master mode, with a 12.288MHz MCLK input being provided? Because it looks like MST_CFG0 register has two writes, one of which seems to be commented out.

//            ADC_DATE_INPUT(0x13 , 0x81);            /*设备配置为 主模式，并且时钟信号（BCLK 和 FSYNC）由外部 MCU 生成*/

              ADC_DATE_INPUT(0x13 , 0x11);            /*设备配置为 从模式，并且时钟信号（BCLK 和 FSYNC）由外部 MCU 生成*/

3) Register 0x15 is a status register, hence read-only.

4) Can you share the redback status of DEV_STS0, DEV_STS1 and ASI_STS (registers 0x15, 0x76 and 0x77) when trying to record on I2S output?

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? ?：

I read the registers you mentioned and the following results:Register address:ASI_STS , register state:ffRegister address:DEV_STS0 , register state:0Register address:DEV_STS1 , register state:c0

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Hi,

ASI_STS = 0xFF indicates invalid FSYNC rate and BCLK-to-FSYNC ratio. Can you also help confirm the other queries listed above?

Thanks and Regards,

Links

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? ?：

1. what should be the value to be written, do you have any suggestion?2. the TLVADC5140 needs to be run in slave mode, with the STM32 as the host, and the ADC is connected to the STM32 with the I2S pin BCLK WS SD no MCLK. 3. I have commented out the 0X15 register.3. I've commented out register 0X15.4. I have read the registers you mentioned and the results are as follows:Register address: ASI_STS , register status: ffRegister address: DEV_STS0 , register status: 0Register address: DEV_STS1 , register status: c0

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Hi,

ASI_STS = 0xFF indicates invalid FSYNC rate and BCLK-to-FSYNC ratio. Can you also help confirm the other queries listed above?

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Links：

The SHDNZ_CFG has valid value of either 0, 1 or 2, so these can be written. 3 is a reserved value, and hence invalid for this field

Regarding 2-4, the ASI_STS is reading as " Invalid sample rate" and "Invalid ratio". Can you confirm the BCLK frequency and sampling rate given from the host? It needs to be as per these conditions.

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z x：

Of course, my sample rate is 48k and BCLK is 1.536MHZ.

,

z x：

Of course, my sample rate is 48k and BCLK is 1.536MHZ.

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