TDA4VL-Q1: OSPI read

HI expert:

There has some questions about TDA4VL OSPI read and write：

The OSPI of TDA4VL was configured as Tap DDR mode. During the signal test, it was found that the Timing Requirements could be met, but the Switching Characteristics timing could not be met.

The software configuration is as follows:

P = CLK cycle time = SCLK period in ns = 20.75MHz ——ns：1/20.75*1000=48.19ns

M = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10

R = refclk cycle time in ns = 166MHz——ns：1/166*1000=6ns

T =OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] = 0

Using the above data and TDA4VL-Q1 to calculate O4 O5 O6, the results are as follows. The measurement timing cannot meet the requirements, but the communication is OK.See those  test pictures:

Two questions need to be answered:
① Does OSPI read refer to the Switching Characteristics sequence?
② The result calculated by the formula is too large, is it the problem of the formula？(I compared the TDA4VM specification, there is no such formula, and the parameters are not calculated to be so large)

Timing：

Switching Characteristics：

Gary Lu：

Hello，

chen qitian 说：① Does OSPI read refer to the Switching Characteristics sequence?

Yes, OSPI read operations do involve switching characteristics, especially the timing of signal transitions between different states. This includes the conversion between clock (CLK) and chip selection (CSn) signals, as well as the conversion between clock and data signals (D [i: 0]).

chen qitian 说：② The result calculated by the formula is too large, is it the problem of the formula

Perhaps the formula you used is not entirely accurate

Regards，

Gary

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chen qitian：

Hi expert:

The formula is from TDA4VL-Q1,is not accurate?and how can i get the true formula,is it any update on the datasheet?

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Gary Lu：

Hello，

This is an errata, please refer to it：https://www.ti.com.cn/cn/lit/pdf/sprz530

Regards，

Gary

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chen qitian：

Hi expert:

I've checked the errata.There is no description of the problem.

Software configuration parameter:

P = CLK cycle time = SCLK period in ns = 20.75MHzM = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10R = refclk cycle time in ns = 166666666T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] =1

Hold time, OSPI0/1_D[7:0] valid after active OSPI0/1_CLK edge

(0.975T(1) (1.84 + R(2)))

=7.69ns

but we test is 4.68ns

Is it the problem of the formula？Please give me the correct formula

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Gary Lu：

Hold time=M×P+N×P+R+T

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chen qitian：

Hi expert:

This hold time formula is ok,

and please give me the correct formula about delay time.

P = CLK cycle time = SCLK period in ns = 20.75MHzM = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10R = refclk cycle time in ns = 166666666T=OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] = 0

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Gary Lu：

Waiting for me to check and reply to you

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Gary Lu：

(P = 20.75 MHz) This is the frequency; to find the period in nanoseconds (ns), you need to take the reciprocal and convert it to ns.(M = 10)(N = 10)(R = 166,666,666 ns) This value seems excessively large for a period in nanoseconds; typically, cycle times are much smaller. Please confirm this value.(T = 0)It appears you have the formulas for delay times \( t_{d(CSn-CLK)} \) and \( t_{d(CLK-D)} \). However, the formulas provided in the image are quite complex, and it is not immediately clear which part refers to the 'hold time' or 'delay time'.If we assume that the hold time formula is correct and you need the delay time formula, we could substitute the given values into the formulas from the image to calculate the delay times.However, there seems to be a misunderstanding with the variable R, as the value given (166,666,666 ns) is extremely high for a clock cycle time. If  R is indeed a cycle time, it should be a much smaller number, since typical clock cycles range from a few nanoseconds to several hundred nanoseconds. The current value of R translates to a period of over 166 seconds, which is not typical for a clock cycle duration. Could you confirm the correct value for R?

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chen qitian：

P = CLK cycle time = SCLK period in ns = 20.75MHz=48.2nsM = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10R = refclk cycle time in ns = 166666666Hz=166MHz=6.02ns

T1 = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] =1T2 =OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] = 0

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Gary Lu：

Please allow me to check, thank you

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Gary Lu：

Hello，

The recalculated delay time value is as follows:For O4 (CSn activation edge to CLK rising edge) and O5 (CLK rising edge to CSn non activation edge), as they have the same formula and both M and N are equal to 10:Minimum delay time (O4_min and O5_min): approximately 80.59 nanosecondsMaximum delay time (O4_max and O5_max): approximately 88.01 nanosecondsFor O6 (CLK activation edge to D [i: 0] conversion), since T2 is 0, DDR reading the delay field does not affect the delay time. The result is:O6 minimum delay time: -17.94 nanosecondsO6 maximum delay time: -1.56 nanosecondsAs with previous calculations, a negative value of O6 means that time is advanced rather than delayed, which is usually physically meaningless. This may indicate that the interpretation of the formula may be incorrect, there may be typing errors in the data manual, or there may be some additional background or compensation that was not captured by the formula itself.Considering the background provided by these formulas and ensuring that there is no other information that may affect their application. Given these results, if there are still differences or confusion, it is best to directly consult the manufacturer's technical support for clear clarification.

Regards，

Gary