ADS5294: 16bits output failed when decimation is enabled

I'm trying to use 16bits outputs with decimaton enabled, but the outputed results (captured with vivado ILA) are NOT correct. Before doing this, I have already tested 16bits output without enabling decimation and got correct 16bits results. 

So here is my question: when decimation is enabled, can we use 16bits format outputs?

Amy Luo：

您好，

这应该是可以16bits 格式输出的，您使用的采样率是多少？是1线LVDS还是2线LVDS？您做了哪些寄存器配置？

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Youhua Xu Xu：

The sampling rate is 78MHz ( driven by a differential clock), and ADS5294 is configured to use 1-wire LVDS outputs. 

The relevant registers are configured as follows:

0X2E ~ 0X35 <= 0b0000_0001_0001_0001

0X38 <= 0b10

0XD1 <= 0X0140

and 0X46 is configured as 

0X46 <= 0b1000_1000_0000_1000

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Amy Luo：

Hi Youhua,

Thank you for providing the information.

Could you tell me what is the frequency of the signal you input?

Thanks,

Amy

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Youhua Xu Xu：

The frequency of the input signal is less than 1MHz. By the way, I also tried to lower the frequency of the input clock to avoid possible timing issues, but the problem still exists…

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Amy Luo：

Hi Youhua,

I will confirm this with a senior engineer and give you an answer tomorrow at the earliest.

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Amy Luo：

A few comments:

1. Can customer set GLOBAL_EN_FILTER = 1 and check?

2. Why is 0XD1 register set to 0X0140? This is not part of the register map. 

3. Can customer try with 14x serialization, instead of 16x serialization? Just to see if the issue goes away. 

4. Is customer seeing this issue only on one device or on multiple devices?

5. Also, customer seems to be going for the Decimation by 4 mode and with DATA_RATE = b10. The output LVDS datarate will reduce by 4x. So essentially, the device will behave like a 78MHz/4 = 19.5MSPS ADC. Just wanted to highlight that in case the customer needs to take care of something on their FPGA firmware. 

6. If customer still sees the issue, can they share the output datastream with decimation and without decimation so that we can look for some clues? 

Thanks,

Amy

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Youhua Xu Xu：

Thanks for forwarding the comments.

1. GLOBAL_EN_FILTER has already been set to 1;

2. 0XD1 is for PLL configuration (see Table 4 of ADS5294 manual)

3. in the case of 14x serialization, I already got the correct outputs.

4. There are two ADS5294 devices in my application, and they are synchronized.

5. I used ramp test @78MHz, and got correct results, so I think my FPGA firmware should be cable of processing data of rate 19.5MSPS

6. I will prepare the output datastream and upload to this place.

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Amy Luo：

waiting for your feedback on point 6 

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Amy Luo：

See the senior engineer comments for each question – 

1. Okay

2. Understood. Sorry, I missed this register setting. You are correct. 

3. Can you elaborate? You mean, you got correct output with 14b, 14x serialization, decimation = 4, Fs = 78MHz? 

4. Okay, you mean you are seeing this issue on both devices?

5. Okay

6. Okay