TI中文支持网Part Number:TMDS1204
We use the TMDS1204 chip, but the input port of TMDS1204 does not have a DDC channel. Therefore, we set the datasheet to DDC disable snoop mode, and TMDS 1204 cannot detect the input signal
jingchao li：
I used the example source code of datasheet
/ (address, data)// Initial power-on configuration.(0x0A, 0x05), // Rate snoop disabled and TXFFE controlled by 35h, 41h, and 42h(0x0B, 0x23), // 3G and 6G tx slew rate control(0x0C, 0x70), // HDMI clock and 8G10G12G TX slew rate control(0x0E, 0x97), // HDMI 1.4, 2.0 and 2.1 CTLE selection(0x11, 0x00), // Disable all four lanes.(0x09, 0x00), // Take out of PD state. Should be done after initialization is complete.// Selection between HDMI modes (1.4, 2.0, and 2.1)switch (HDMI_MODE) {case 'HDMI14_165' : // HDMI 1.4 configuration for less than 1.65 Gbps(0x11, 0x00), // Disable all four lanes.(0x0D, 0x20), // Limited mode, DC-coupled TX, 0dB DCG, Term open, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x00), // Clock lane EQ.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x00), // Disable FRL(0x11, 0x0F), // Enable all four lanes.break;case 'HDMI14_340' : // HDMI 1.4 configuration for greater than 1.65 Gbps(0x11, 0x00), // Disable all four lanes.(0x0D, 0x21), // Limited mode, DC-coupled TX, 0dB DCG, Term 300, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x00), // Clock lane EQ.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x00), // Disable FRL(0x11, 0x0F), // Enable all four lanes.break;case 'HDMI20' : // HDMI 2.0 configuration(0x11, 0x00), // Disable all four lanes.(0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x00), // Clock lane EQ.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x02), // Set TMDS_CLK_RATIO(0x31, 0x00), // Disable FRL(0x11, 0x0F), // Enable all four lanes.
break;case 'HDMI21_3G' : // HDMI 2.1 3 Gbps FRL(0x11, 0x00), // Disable all four lanes.(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x00), // Clock lane EQ.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x01), // Set to 3G FRL. Only TXFFE0 supported.(0x11, 0x0F), // Enable all four lanes.break;case 'HDMI21_6G_3lane' : // HDMI 2.1 6 Gbps FRL 3 lanes(0x11, 0x00), // Disable all four lanes.(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x00), // Clock lane EQ.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x02), // Set to 6G FRL and 3 lanes. Only TXFFE0 supported.(0x11, 0x0F), // Enable all four lanes.break;case 'HDMI21_6G_4lane' : // HDMI 2.1 6 Gbps FRL 4 lanes(0x11, 0x00), // Disable all four lanes.(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x0Y), // Clock lane EQ. Set to "Y" to desired value.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x03), // Set to 6G FRL and 4 lanes. Only TXFFE0 supported.(0x11, 0x0F), // Enable all four lanes.break;case 'HDMI21_8G' : //HDMI 2.1 8 Gbps FRL(0x11, 0x00), // Disable all four lanes.(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x04), // Set to 8G FRL and 4 lanes. Only TXFFE0 supported.(0x11, 0x0F), // Enable all four lanes.break;case 'HDMI21_10G' : //HDMI 2.1 10 Gbps FRL(0x11, 0x00), // Disable all four lanes.(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x05), // Set to 10G FRL and 4 lanes. Only TXFFE0 supported.(0x11, 0x0F), // Enable all four lanes.break;
case 'HDMI21_12G' : //HDMI 2.1 12 Gbps FRL(0x11, 0x00), // Disable all four lanes.(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass(0x12, 0x03), // Clock lane VOD and TXFFE(0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.(0x14, 0x03), // D0 lane VOD and TXFFE.(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.(0x16, 0x03), // D1 lane VOD and TXFFE.(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.(0x18, 0x03), // D2 lane VOD and TXFFE.(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.(0x20, 0x00), // Clear TMDS_CLK_RATIO(0x31, 0x06), // Set to 12G FRL and 4 lanes. Only TXFFE0 supported.(0x11, 0x0F), // Enable all four lanes.break;}
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Kailyn Chen：
Hello， about your questions, I need some times to confirm.
And I would reply you as soon as possiable.
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jingchao li：
Our application method is as follows：
There is no DDC channel between FPGA and TMDS1204
Source（HDMI2.1）-> ITE hdmi2.1 IC->FPGA->TMDS1204->ITE hdmi2.1 IC
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jingchao li：
so we want to use limited redriver mode of TMDS204 without snoop DDC
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Kailyn Chen：
Is this a source or a sink side design? Can you share the TMDS1204 portion of the schematic?
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jingchao li：
I have already sent you an email
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Kailyn Chen：
I haven‘t receive your Email yet.
Or you could send it with private message. I have sent the friend request over forum, please approve and you could sent the schematic to me.
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jingchao li：
ok、
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jingchao li：
Do you have any news？
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jingchao li：
Why hasn't someone provided technical support for TI?
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Kailyn Chen：
I have sent you with private message, and I will reply you as soon as possible.
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jingchao li：
When can the IT engineer give a response？
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Kailyn Chen：
Hello，
SIGDET_OUT requires a 10k or greater pull-up resistor.
Please remove the pull up on EN, and have a 0.1uF or 0.22uF capacitor on the EN pin for the proper reset.
LV_DDC_SCL and LV_DDC_SDA should left floating if not used.
If you write a value of 0x06 to register 0x09, are you able to see the TMDS1204 output?
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jingchao li：
1. We are testing 1920*1080*60Hz TMDS without any issues, and SIGDET_ OUT pin can detect input signals normally， and the monitor can output images normally
2.We are testing 3840*2160*60Hz TMDS without any issues, and SIGDET_ OUT pin can detect input signals normally and the monitor can output images normally
3. When we using FRL 8G (7680*3840*30Hz)，SIGDET_ OUT pin can detect input signals normally，but the TMDS1204 has not output. Why?
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Kailyn Chen：
Hello，
Is HPD_SNK being driven high for FRL 8G resolution?
Can you dump out all TMDS1204 registers when doing FRL 8G resolution?
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jingchao li：
1. HPD is High when FRL 8G resolution
2. Can you provide some feasible suggestions or do you have TI professional technical support
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Kailyn Chen：
I have escalated your question to our senior engineer who is specified for this IC yesterday ,he suggested you could dump all TMDS1204 registers to check.
