TMS320C6678: EDMA3读取Local L2 SRAM

Part Number:TMS320C6678

The L2 memory configuration for the C6678 device is as follows: • Total memory size is 4096KB • Each core contains 512KB of memory • Local starting address for each core is 0080 0000h L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.

Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses. For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000, for C66x CorePac Core 1 this is equivalent to 0x11800000, and for C66x CorePac Core 2 this is equivalent to 0x12800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.




#define L2_1_FirstAddr (char *)0x10800000
#define L2_1_EndAddr (char *)0x1080ffff
#define L2_2_FirstAddr (char *)0x10810000
#define L2_2_EndAddr (char *)0x1081ffff
#define MSMC_1_FirstAddr (char *)0x0c100000
#define MSMC_1_EndAddr (char *)0x0c10ffff
#define MSMC_2_FirstAddr (char *)0x0c110000
#define MSMC_2_EndAddr (char *)0x0c11ffff
#define DDR_1_FirstAddr (char *)0x80000000
#define DDR_1_EndAddr (char *)0x8000ffff
#define DDR_2_FirstAddr (char *)0x80100000
#define DDR_2_EndAddr (char *)0x8010ffff

DMA_ParaConfig( 0, 0 ,0x80000000 ,0Xffff, 0X1, 0x10800000 ,0XFFFFFFFF);

// DMA0部件 2通道
DMA_Start( 0 , 0);

// DMA0部件 2通道
// 返回DMA传输状态,1表示数据传输已结束,0表示未结束。
while (!DMA_TransState( 0 , 0));




Gary Lu:



Gary Lu:

Huang Fujun said:EDMA3可以读取0x00800000这片地址的内存数据吗?

是的,EDMA3 可以读取内存地址 0x00800000 处的数据。

专门为测试 EDMA3 创建了两个常见问题解答


1. 如何进行 EDMA3 PING PONG 测试。-  https://www.ti2k.com/wp-content/uploads/ti2k/DeyiSupport_DSP_faq-tms320c6678-how-to-create-a-edma-ping-pong-test-code-using-the-csl-chip-support-library-package-and-test-on-c6678-evm -csl-chip-support-library-package-and-test-on-c6678-evm

2. DDR3_EDMA 测试 –  https://www.ti2k.com/wp-content/uploads/ti2k/DeyiSupport_DSP_faq-tms320c6678-ddr3-read-write-test-code-or-how-to-do-ddr3-test-on-c6678-evm-or-k2h-evm-board -do-ddr3-test-on-c6678-evm-or-k2




/* 内存映射 */MEMORY{    L2SRAM (RWX) : org = 0x00800000, len = 0x080000    MSMCSRAM (RWX) : org = 0x0c000000, len = 0x200000    DDR3A (RWX) : org = 0x80000000, len = 0x1000000 0}



/************************************************************************************** DDR3A EDMA Config* This function configures the QDMA in the EDMA for burst access. The physical address* of the source/destination, and the size of the transfer block are given in the* function parameters.*-----------------------------------------------------------------------------------*/
void ddr3_edma_config(unsigned int src, unsigned int dst, unsigned int nbytes)
{unsigned int acnt = nbytes;unsigned int bcnt = 1;unsigned int ccnt = 1;// Clear the pending interruptEDMA_ICR = 0x1;// QDMA channel 0 uses parameter set 0, trigger word 7EDMA_QCHMAP0 = 0x1C;

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