TI中文支持网Part Number:AFE5818
In LVDS test mode, all 0, all 1, 01 alternate, 11111110000000 and custom modes can run normally, but the frame clock captured by configured ramp, toggle, prbs mode and ila will be out of alignment, and the collected data will be wrong. What is the cause? Do you need TX_TRIG clock signals to configure ramp, toggle and prbs?
Alice：
您好， 已经收到了您的案例，调查需要些时间，感谢您的耐心等待。
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Lydia：
Hi,
From device side it should be aligned . This mismatch can come due to latency mismatch in the board/FPGA . So such situations customer should take care in fpga .
To verify device is behaving correctly customer can probe directly at the dout and fclk .
