TI中文支持网Part Number:LMX2492
Our frequency synthesizer configuration is LMX2492+CHC2442, generating a Chirp signal with a time interval of 204us and a bandwidth of 50MHz. Our concern is that within the 204us duration, we need to traverse the entire 50MHz bandwidth. Does the LMX2492 need to perform frequency locking for each frequency point? It is known that the locking time for a single frequency point with LMX2492 is around 100us. How can we achieve frequency locking for each frequency point within the 204us duration? Clearly, the locking time is not allowed. Additionally, could you please explain the generation mechanism and specific working principle of the Chirp signal using LMX2492? Thank you very much!
Cherry Zhou：
Hi,
Our expert is looking into this issue, please expect the response.
Thanks.
,
Cherry Zhou：
Hi,
Please see the response below:
I don't think of it as locking, but more as slewing. So it does not need to perform frequency locking at every step. The ramp updates the frequency every 1/Fpd time steps, so this is way faster than the PLL could lock.
The way that this works is it ramps the fractional numerator in the N divider, so it has to go through the loop filter. In this way, it limits the slew rate, but 50 MHz in 204 us or about 0.25 MHz/us should be no issue.
