LMX2492: 50MHz/204us Chirp Linearity Quality Improvement

For Chirp signal genenrated by LMX2492+CHC2442, frequency .vs. time Chirp Linearity is critical for our application.  However, Suggested by some experience, the actul generated Chirp Linearity quality would be affected by Loop filter configuration and Charge Pump Gain , by the same Loop filter configuration, Chirp Linearity would be better with higher Charge Pump Gain, but phase noise would be accordingly degraded. we also have several Chirp Ramping segments tried, but it seems no obvious Linearity improvement on Chirp signal with a time interval of 204us and a bandwidth of 50MHz.  TI official PLL design tool of "TICS Pro" is effective for single CW frequency locking configuration, but we have no idea on how to improve Chirp Linearity with it.  Considering Chirp Linearity could be the transcient responses, the design guidance is missing for the best Chirp Linearity quality achievment.  so would you please present us the guidance on Chirp Linearity improvement with better phase noise simultanouly, it should inculde Loop filter configuration, Charge Pump Gain, chirp raming segments and other factors not mentioned. it is very hopefully to be effective.  very looking forwardws to your prompt reply.  Thanks!

Cherry Zhou：

Hi,

Please allow some time to get back to you.

Thanks.

,

Cherry Zhou：

Hi,

The TICSPRO is a very good tool for setting up these ramps, but does not design the loop filter.  The PLLatinum Sim tool (ti.com/tool/PLLATINUMSIM-SW) does this.

If the loop bandwidth is too narrow, then the linearity will be worse.  Also, when you have a sharp abrupt from a chirp that goes down in frequency, this can cause some issues.

You might find this article useful.

,

? ??：

Thanks for you reply, However, it is known that "PLLatinum Sim tool" is about to design the loop filter.However, our point is about to how to improve Chirp Linearity, it is known that associated design guidance is missing for the best Chirp Linearity quality achievement.  so would you please present us the guidance on Chirp Linearity improvement with better phase noise simultaneously, it should include Loop filter configuration, Charge Pump Gain, chirp ramping segments and other factors not mentioned. it is very hopefully to be effective.  very looking forwards to your prompt reply.  Thanks!

,

Cherry Zhou：

Hi,

You may find this application note useful:

https://www.planetanalog.com/optimizing-loop-filter-bandwidth-for-modulated-pll-ramping-waveforms/?page_number=2

Also, in reference to providing Loop filter configuration, Charge Pump Gain, chirp ramping segments, we would need:

1.  Input reference frequency

2.  Ramp starting frequency

,

? ??：

thank you for your reply, we have cited paper carefully read, however, it has chirp generation formula introduced and present a actual LMX2942 chirp generation samples, for our concerned questions on how to improve Chirp Linearity, it seems not to have answers.However, our point is about to how to improve Chirp Linearity, it is known that associated design guidance is missing for the best Chirp Linearity quality achievement.  so would you please present us the guidance on Chirp Linearity improvement with better phase noise simultaneously, it should include Loop filter configuration, Charge Pump Gain, chirp ramping segments and other factors not mentioned. it is very hopefully to be effective.  very looking forwards to your prompt reply.  Thanks!

,

? ??：

thanks for your suggestions on Chirp Linearity improvement is about to  increase the loop bandwidth of the loop flter.  However, we have loop bandwidth of 600KHz/800KHz/1MHz tried and do find the FRAC_Order and Charge Bump Gain have impacts on the phase noise and Chirp Linearity performance.  Considering the Charge Bump Gain modification, as you also mentioned, would have loop bandwidth affected, so it seems that Chirp Linearity improvement is complex than expected,  would you please present us more guidance on Chirp Linearity improvement with better phase noise simultaneously, it should include Loop filter configuration, Charge Pump Gain, chirp ramping segments and other factors not mentioned. it is very hopefully to be effective.  very looking forwards to your prompt reply.  Thanks!

,

Cherry Zhou：

You have not provided the input reference frequency or ramp starting frequency, so I will asssume someting based on our LMX2594 EVM.

Instructions are at:  www.ti.com/…/snau160e.pdf

It is incorrect to say that a higher charge pump gain will degrade phase noise.  PLL phase noise improves with higher charge pump gain and it allows a wider loop bandwidth.  However, if you just increase the charge pump gain without re-designing the loop filter, you might see an unoptimized resuit and this is what might give the false impression that designing for a higher charge pump current degrades phase noise.

Input Reference Frequency = 100 MHz

Ramping  Start Frequency: 10000 MHz

Ramping Stop Frequency:  10050 MHz

VCO Gain:  240 MHz/V

So what I did was take the LMX2492 EVM design and increase the loop bandwidth for better linearity.  Then I created a 50 MHz chirp that is 204 us long on TICSPRO  (I didn't measure though).  Attached is the PLLatinum Sim file, TICSPRO file, and some pictures.

To improve the chirp linearity, my proposal is the increase the loop bandwidth of the loop filter.  Attached some screenshots from PLLatinim Sim and TICSPRO.

,

? ??：

thanks for your suggestions on Chirp Linearity improvement is about to  increase the loop bandwidth of the loop flter.  However, we have loop bandwidth of 600KHz/800KHz/1MHz tried and do find the FRAC_Order and Charge Bump Gain have impacts on the phase noise and Chirp Linearity performance.  Considering the Charge Bump Gain modification, as you also mentioned, would have loop bandwidth affected, so it seems that Chirp Linearity improvement is complex than expected,  would you please present us more guidance on Chirp Linearity improvement with better phase noise simultaneously, it should include Loop filter configuration, Charge Pump Gain, chirp ramping segments and other factors not mentioned. it is very hopefully to be effective.  very looking forwards to your prompt reply.  Thanks!

,

Cherry Zhou：

Hi,

Linearity and phase noise are contradict to each other. To get better linearity, we need higher loop bandwidth. However, once we open wide the loop, fractional spurs problem will get worst. As a result, phase noise is bad.

If you need both, you may consider use a DAC to control the VCO frequency, however, you will lose frequency accuracy.

Be practical and realistic, good linearity and good phase noise don't exist at the same time.

Above response has provided an example design, please try it and get back to us the test result if you think linearity is still not enough. 

Please see the link below to get the response from our expert:

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1255790/lmx2492-50mhz-204us-chirp-linearity-quality-improvement/4770201#4770201