TI中文支持网Part Number:TMS320F280049C
I have read some examples which introduce trip zone. But the examples are to turn off EPWM after TZ1 is triggered and goes to interrupt.
Is it necessary to turn off EPWM in the interrupt function? Will interrupt delay the time, how long will it take?
Is it possible to set the register directly to "once TZ is triggered, epwm will no longer pull up"? My current experimental waveform will still pull up in the next cycle, or mask out a section during the high period, which does not meet the expectations of OSHT, and my configuration is as follows:
Part of CMPSS: (CMPSS1_L:)
/*CMP1_L for OCP */Cmpss1Regs.CTRIPLFILCTL.bit.SAMPWIN = 3;//Digital ilterCmpss1Regs.CTRIPLFILCTL.bit.THRESH = 2;Cmpss1Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 0;Cmpss1Regs.CTRIPLFILCTL.bit.FILINIT = 1;Cmpss1Regs.COMPSTSCLR.bit.LLATCHCLR = 1;//CMP_H:High comparator latch software clear//CTRIPOUTH = CLBX-BAR INPUTSCmpss1Regs.COMPCTL.bit.CTRIPOUTLSEL = 2; //Output of digital filter drives CTRIPOUTHCmpss1Regs.COMPCTL.bit.CTRIPLSEL = 2; //Output of digital filter drives CTRIPHCmpss1Regs.COMPCTL.bit.COMPLINV = 1; //Output of comparator is not invertedCmpss1Regs.COMPCTL.bit.COMPLSOURCE = 0;//Inverting input of comparator driven by internal DACCmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 0;//DACxVALA is updated from DACxVALS on EPWMSYNCPER//Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0;//DACHVALA is updated from DACHVALSCmpss1Regs.DACLVALS.bit.DACVAL = 4000;
Then output to GPIO3 through OutputXbar, GPIO3 is connected to GIO16 in hardware, and GPIO16 is configured as InputXBar for TZ1
In the EPWM section, configure TZ1 as OSHT and hope to Force down EPWM1A and EPWM2A at the same time:
//TZ1 -> OCPEPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;//Enable TZ1 as a one-shot trip source for this ePWM moduleEPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;//Set the trip action on TZ1 to force ePWM1 lowEPwm1Regs.TZCLR.bit.OST = 1;// Clear TZ1 one-shot trip flagEPwm1Regs.TZFRC.bit.OST = 1;// Force TZ1 one-shot trip//TZ1 -> OCPEPwm2Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;//Enable TZ1 as a one-shot trip source for this ePWM moduleEPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;//Set the trip action on TZ1 to force ePWM1 lowEPwm2Regs.TZCLR.bit.OST = 1;// Clear TZ1 one-shot trip flagEPwm2Regs.TZFRC.bit.OST = 1;// Force TZ1 one-shot trip
EPWM1A/2A each have DCAEVT1.sync and DCAEVT2.force, so that's why the current sensor results after the internal comparator connected out and in for TZ1, this more troublesome way. Considering that TZ is active low, has reversed the comparator output results.
I would like to implement a fast overcurrent protection with TZ OSHT. I hope you can point out where there is a problem, thanks! Is it necessary to add interrupts？
Thanks!
Ginger：
Is DCAEVT1(which is OSHT naturally) can't exist with TZ1(which is configure as one shot trip)?
Because EPwm1Regs1.TZCLR.bit.OST=1 will clear both of them? Can they work independently?
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Ginger：
I found that I have use DCAETV1.sync every cycle, and "EPwm1Regs1.TZCLR.bit.OST=1" to clear OST latch every cycle. So this is why my TZ1 didn't work.
But now, how I can enable the DCAETV1.sync every cycle like before, and at the same time to enable the TZ1(OST1) to protect my circuit?
,
Yale Li：
Ginger 说：
But the examples are to turn off EPWM after TZ1 is triggered and goes to interrupt.
Is it necessary to turn off EPWM in the interrupt function? Will interrupt delay the time, how long will it take?
After correct configurations, the output waveform of EPWM can be automatically turned off by TZ sub-module. So there is no delay which is generated by code running. You can operate other operations during TZ ISR.
Pls notice TZCTL Register in sprui33f_TMS320F28004x Real-Time Microcontrollers Technical Reference Manual (Rev. F) P2016:
