AM5708: sram问题咨询

在手册《AM570x Sitara Processors datasheet (Rev. F).pdf 》 第6.4 DSP Subsystem章节提到

A 32-KiB L1 data memory (L1D) configurable as cache and / or SRAM:
• When configured as a cache, the L1D is a 2-way set-associative cache with a 64-byte cache
line
• The DSP CorePac L1D memory controller provides bandwidth management, memory
protection, and power-down functions
• The L1D memory can be fully configured as a cache or SRAM
• No support for error correction or detection
• Page size for L1D memory is 2KB