TMS320F28062: AQCSFRC采用影子寄存器模式，波形还是不完整

EPwm1配置为增减计数模式

EPwm1Regs.AQSFRC.bit.RLDCSF = 0; //conter = zero时load

在增减计数的任意时刻写入EPwm1Regs.AQCSFRC.all = 0x0;或者EPwm1Regs.AQCSFRC.all = 0x1;出现脉宽不完整的情况

Green Deng：

你好，脉宽不完整具体是什么情况？能否给个图示指明一下。

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Chao Yan：

比如我想封波的时候写EPwm1Regs.AQCSFRC.all = 0x1;按理来说应该在counter = zero，AQCSFRC从shadow 加载的下个时钟沿生效，之后不会出现高电平，现在却是会多出一个不完整的脉冲

,

Green Deng：

程序中有没有设置死区？互补PWM输出？

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Chao Yan：

没有用死区，也没有互补输出，以下是初始化代码

EPwm1Regs.TBCTR = 0;
u16Status = SFO_INCOMPLETE;
while(u16Status == SFO_INCOMPLETE)// Call until complete
{u16Status = SFO();// exceeds maximum of 255.if(u16Status == SFO_ERROR){ESTOP0;// Stop here and handle error}
}
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Stop all the TB clocksEPwm1Regs.TBCTR = 0;// clear
EPwm1Regs.TBPRD = cPwmPrd;// 200K
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// 增减计数模式
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;// TBCTR不从TBPHS装载
EPwm1Regs.TBPHS.half.TBPHS = 0;// TBPHS值
EPwm1Regs.TBPHS.half.TBPHSHR = 0;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// (当TBCTR=0时)TBPRB从影子寄存器装载
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;// TBCTR=0---作为同步事件
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;//比较计数模块
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;// (当TBCTR=0时)CMPA装载
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;// (当TBCTR=0时)CMPB装载
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;// Shadow mode 选择影子寄存器模式
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;// Shadow mode 选择影子寄存器模式
EPwm1Regs.CMPA.half.CMPA =188;// 初始比较值
EPwm1Regs.CMPA.half.CMPAHR = (1 << 8);// initialize HRPWM extension
EPwm1Regs.CMPB = 220;//EPwm1Regs.AQSFRC.bit.RLDCSF = 0;// (立即装载)AQSFRC寄存器从影子寄存器装载
EPwm1Regs.AQCSFRC.all = 0x01;// PWMxA force low
EPwm1Regs.AQCTLA.all = 0;
EPwm1Regs.AQCTLB.all = 0;EPwm1Regs.AQCTLA.bit.CBD = AQ_SET;// TBCTR=TBPRD时PWMxA输出高
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;// TBCTR=CMPA 且TBCTR减计数时PWMxA输出低
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;// TBCTR=TBPRD时PWMxB输出高
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;// TBCTR=CMPB 且TBCTR减计数时PWMxB输出低//死区生成子模块
EPwm1Regs.DBCTL.bit.OUT_MODE = 0x00;// ePWMxA/xB信号均跳过死区子模块
EPwm1Regs.DBCTL.bit.POLSEL = 0x00;// ePWMxA/xB信号均不取反
EPwm1Regs.DBFED = 0;//TZ模块
EPwm1Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;// 当Trip事件发生时,PWMxA强制输出低
EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;//PWMxB
EPwm1Regs.TZSEL.bit.OSHT1 = 1;// 使能TZ1作为首发脉冲故障信号EPwm1Regs.TZEINT.bit.OST = 1;// 使能TZ首发脉冲故障中断
EPwm1Regs.TZCLR.bit.INT = 1;
EPwm1Regs.TZCLR.bit.OST = 1;//事件触发模块
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;// 选择TBCTR=0作为事件
EPwm1Regs.ETSEL.bit.INTEN = 0;// 禁止中断
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;// 每次事件产生一个中断//事件触发模块
EPwm1Regs.ETSEL.bit.SOCAEN = 1;// 使能ePWMxSOCA启动AD转换
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTRD_CMPA;// 选择CTR=CMPB且TBCTR减计数作为事件,触发ePWMxSOCA信号
EPwm1Regs.ETPS.bit.SOCAPRD = ET_2ND;// 每2次事件触发一个ePWMxSOCA信号----300KHz开关频率,100KHz控制频率EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP;// MEP control on falling edge
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm1Regs.HRCNFG.bit.HRLOAD= HR_CTR_ZERO;#if (AUTOCONVERT)
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;// Enable auto-conversion logic#endif
EPwm1Regs.HRPCTL.bit.HRPE = 0;// Turn off high-resolution period control.

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Green Deng：

试一下把这部分代码

EPwm1Regs.AQSFRC.bit.RLDCSF = 0;// (立即装载)AQSFRC寄存器从影子寄存器装载
EPwm1Regs.AQCSFRC.all = 0x01;// PWMxA force low

放到这部分代码后面呢？

EPwm1Regs.AQCTLA.bit.CBD = AQ_SET;// TBCTR=TBPRD时PWMxA输出高
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;// TBCTR=CMPA 且TBCTR减计数时PWMxA输出低
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;// TBCTR=TBPRD时PWMxB输出高
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;// TBCTR=CMPB 且TBCTR减计数时PWMxB输出低

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Chao Yan：

EPwm1Regs.AQCTLA.bit.CBD = AQ_SET;// TBCTR=TBPRD时PWMxA输出高
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;// TBCTR=CMPA 且TBCTR减计数时PWMxA输出低
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;// TBCTR=TBPRD时PWMxB输出高
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;// TBCTR=CMPB 且TBCTR减计数时PWMxB输出低

上面这段，只在初始化的时候设置了，其他地方没有更改

EPwm1Regs.AQCSFRC.all = 0x01;只在中断里面经常调用

波形不完整的现象极少出现，大部分时候还是能起作用的

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Chao Yan：

问题已解决，软件和硬件共同的问题，非常感谢你的回答