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TLV320AIC3254使用的问题

DSP用TLV320AIC3254,主控芯片接的是EVM板,IIS音频数据输入正常,IIC通讯正常,用以下代码跑程序,发现IIS音频输入模式,喇叭和耳机都无音频输出;

AUX音频输入模式,喇叭无声,耳机有声,但是声音很小和很多杂音。

请帮忙看看以下设置哪里设置有问题。

static const reg_value REG_Section_program[] = {
{ 0,0×00},
//Initialize the device through software reset
{ 1,0×01},
//—————– { 0,0×01},
//Power up AVDD LDO; Disable weak AVDD to DVDD connection; Enable Master Analog Power Control, AVDD LDO Powered; Disable weak AVDD to DVDD connection
{ 1,0×08},
//Enable Master Analog Power Control
{ 2,0×00},
//Set the input power-up time to 3.1ms
{ 71,0×32},
//Set REF charging time to 40ms (automatic)
{123,0×01},
#if 0
//Set miniDSP_A_reg {255,0×00},
//Set miniDSP_D_reg
{255,0×01},
#endif
//—————– { 0,0×00},
//miniDSP_A and miniDSP_D are independently powered up//miniDSP_D used for signal processing
{ 60,0×00},
//miniDSP_A used for signal processing
{ 61,0×00},
//8x Interpolation
{ 17,0×08},
//4x Decimation
{ 23,0×04},
// { 15,0×03},
// { 16,0×88},
// { 21,0×03},
// { 22,0×88},
//—————– { 0,0×08},
//adaptive mode for ADC
{ 1,0×04},
//—————– { 0,0x2C},
//adaptive mode for DAC
{ 1,0×04},
//—————– { 0,0×00},
//P=1, R=1, J=8
{ 5,0×91},
//P=1, R=1, J=8
{ 6,0×08},
//D=0000 (MSB)
{ 7,0×00},
//D=0000 (LSB)
{ 8,0×00},
//PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
{ 4,0×03},
//MDAC = 8, divider powered on
{ 12,0×88},
//DOSR = 128 (MSB)
{ 13,0×00},
//DOSR = 128 (LSB)
{ 14,0×80},
//NADC = 2, divider powered on
{ 18,0×82},
//MADC = 8, divider powered on
{ 19,0×88},
//AOSR = 128
{ 20,0×80},
//NDAC = 2, divider powered on
{ 11,0×82},
#if 0
//Interface = I2S, Length = 20bits, BCLK and WCLK output
{ 27,0x1C},
//BDIV_CLKIN = DAC_MOD_CLK
{ 29,0×01},
//BCLK power up, BCLK N divider = 2
{ 30,0×82},
#else
//Interface = I2S, Length = 16bits, BCLK and WCLK input
{ 27,0×00},
#endif
//—————–
{ 0,0×01},
//Mic Bias enabled, Source = Avdd, 1.25V
{ 51,0×40},
#if 0//Route IN1L to LEFT_P with 10K input impedance;
{ 52,0×40},
//Route CM1L to LEFT_M with 10K input impedance
{ 54,0×40},
//Route IN1R to RIGHT_P with 10K input impedance
{ 55,0×40},
//Route CM1R to RIGHT_M with 10K input impedance
{ 57,0×40},
#else
//IN2L is routed to Left MICPGA with 20k resistance
{ 52,0×20},
//CM is routed to Left MICPGA via CM1L with 20k resistance
{ 54,0×80},
//IN2R is routed to Right MICPGA with 20k resistance
{ 55,0×20},
//CM is routed to Right MICPGA via CM1R with 20k resistance
{ 57,0×80},#endif
//Enable MicPGA_L Gain Control, 0dB
{ 59,0×00},
//Enable MicPGA_R Gain Control, 0dB
{ 60,0×00},
//—————– { 0,0×00},
//Power up LADC/RADC
{ 81,0xC0},
//Unmute LADC/RADC
{ 82,0×00},
//—————– { 0,0×01},
//De-pop: 5 time constants, 6k resistance
{ 20,0×25},
//Route LDAC to HPL
{ 12,0×08},
//Route RDAC to HPR
{ 13,0×08},
//Route LDAC to LOL
{ 14,0×08},
//Route LDAC to LOR
{ 15,0×08},
//—————– { 0,0×00},
//Power up LDAC/RDAC w/ soft stepping
{ 63,0xD4},
//—————– { 0,0×01},
//Unmute HPL driver, 0dB Gain
{ 16,0×00},
//Unmute HPR driver, 0dB Gain
{ 17,0×00},
//Unmute LOL driver, 0dB Gain
{ 18,0×00},
//Unmute LOR driver, 0dB Gain
{ 19,0×00},
//Power up HPL/HPR and LOL/LOR drivers
{ 9,0x3C},
//—————– { 0,0×00},
//Unmute LDAC/RDAC
{ 64,0×00},
//Unmute LADC , Fine Gain 0dB; Unmute RADC , Fine Gain 0dB
{ 82,0×00},
//Left ADC Channel Volume = 0.0dB
{ 83,0×00},
//Left Channel AGC Target Level = -12.0dBFS ; Gain Hysteresis is ±1.0dB
{ 86,0×20},
//Left Channel AGC Hysteresis is disabled ; Noise Threshold is -88dB
{ 87,0xFE},
//Left Channel AGC Maximum Gain = 0.0dB
{ 88,0×00},
//Left Channel AGC Attack Time = 13 * 32 ADC Word Clocks
{ 89,0×68},
//Left Channel AGC Decay Time = 17 * 512 ADC Word Clocks
{ 90,0xA8},
//Left Channel AGC Noise Debounce Time = 64 ADC Word Clocks
{ 91,0×06},
//
{ 92,0×00},
//Right ADC Channel Volume = 0.0dB { 84,0×00},
//
{ 94,0×20},
//
{ 95,0xFE},
//
{ 96,0×00},
//
{ 97,0×68},
//
{ 98,0xA8},
//
{ 99,0×06},
//
{100,0×00},
};

Nancy Wang:

请去音频论坛咨询。
e2echina.ti.com/…/

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