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dsp 6678 多核spi boot过程中修改主核和从核的cmd文件导致原本连仿真器可以正常运行的程序跑飞

问题如题,具体情况如下:用到了核0,1,2,3,4这一共5个核,核0作为主核,其他四个核是从核

主核(核0)cmd文件:主要的想法是把主核的程序放在主核的L2上,其他数据段放在DDR上,并且boot起始地址也按照论坛里说的指定为0x10800000

-x
-stack 0x10000
-heap 0x10000

MEMORY
{

VECTORS: origin = 0x00800000 length = 0x00000400
/*Local addresses*/
//LL2MEM: origin = 0x00800400 length = 0x0007FC00

/* M3 RAM */
MSMCRAM: origin = 0x0C000000 length = 0x00400000
DDR3RAM: origin=0x80000000 length=0x20000000 /*512*/

BOOT_CORE0: origin = 0x10800000 length = 0x000000c0
CORE0_L2: origin = 0x108000c0 length = 0x0007FF40
CORE0_DDR3: origin=0xa0000000 length=0x10000000

BOOT_CORE1: origin = 0x11800000 length = 0x000000c0
CORE1_L2: origin = 0x118000c0 length = 0x0007FF40
CORE1_DDR3: origin=0xb0000000 length=0x10000000

BOOT_CORE2: origin = 0x12800000 length = 0x000000c0
CORE2_L2: origin = 0x128000c0 length = 0x0007FF40
CORE2_DDR3: origin=0xc0000000 length=0x10000000

BOOT_CORE3: origin = 0x13800000 length = 0x000000c0
CORE3_L2: origin = 0x138000c0 length = 0x0007FF40
CORE3_DDR3: origin=0xd0000000 length=0x10000000

BOOT_CORE4: origin = 0x14800000 length = 0x000000c0
CORE4_L2: origin = 0x148000c0 length = 0x0007FF40
CORE4_DDR3: origin=0xe0000000 length=0x10000000
}
SECTIONS
{
.csl_vect: > VECTORS

/* Boot Memory Sections */
//.boot: > LL2MEM

/* Text Memory Sections */
.text: > CORE0_L2
.DDRText{MulticoreBoot.obj(.text)}>CORE0_L2
.stack: > CORE0_L2

/* Data Memory Sections */
.data: > CORE0_DDR3
.cinit: > CORE0_DDR3
.bss: > CORE0_DDR3
.const: > CORE0_DDR3
.far: > CORE0_DDR3
.switch: > CORE0_DDR3
.sysmem: > CORE0_DDR3
.cio: > CORE0_DDR3

.heap > CORE0_DDR3
// .fardata > LL2MEM
// .neardata > LL2MEM
//.rodata > LL2MEM

//.INRAM > LL2MEM
//.MSRAM > MSMCRAM
//.EXRAM > DDR3RAM
.myboot
{
*.*<boot.obj>(.text)

} > BOOT_CORE0
}

几个从核的CMD文件如下:boot地址指定为0x1x800000,其他程序核数据段全放在DDR上。

-x
-stack 0x3200000
-heap 0xC800000 //50M 3200000

MEMORY
{

//VECTORS: origin = 0x00800000 length = 0x00000400
/*Local addresses*/
//LL2MEM: origin = 0x00800400 length = 0x0007FC00

/* M3 RAM */
//MSMCSRAM: origin = 0x0C000000 length = 0x00200000

VECTORS: origin = 0x00800000 length = 0x00000400
/*Local addresses*/
LL2MEM: origin = 0x00800400 length = 0x0007FC00

/* M3 RAM */
MSMCRAM: origin = 0x0C000000 length = 0x00200000
DDR3RAM: origin=0x80000000 length=0x20000000 /*512*/

BOOT_CORE0: origin = 0x10800000 length = 0x000000c0

BOOT_CORE1: origin = 0x11800000 length = 0x000000c0
CORE1_DDR3: origin=0xa0000000 length=0x15e00000
BOOT_CORE2: origin = 0x12800000 length = 0x000000c0
CORE2_DDR3: origin=0xb6000000 length=0x15e00000
BOOT_CORE3: origin = 0x13800000 length = 0x000000c0
CORE3_DDR3: origin=0xcc000000 length=0x15e00000
BOOT_CORE4: origin = 0x14800000 length = 0x000000c0
CORE4_DDR3: origin=0xe2000000 length=0x15e00000
}
SECTIONS
{
.csl_vect: > VECTORS

/* Boot Memory Sections */

.myboot
{
*.*<boot.obj>(.text)

} > BOOT_CORE1

/* Text Memory Sections */
.text: > CORE1_DDR3

/* Data Memory Sections */
.data: > CORE1_DDR3
//程序段
.fasttext: > CORE1_DDR3
.cinit: > CORE1_DDR3
.const: > CORE1_DDR3
.switch: > CORE1_DDR3
.cio: > CORE1_DDR3
.heap > CORE1_DDR3
//数据段
.stack: > CORE1_DDR3
.bss: > CORE1_DDR3
.far: > CORE1_DDR3
.sysmem: > CORE1_DDR3

.fardata > CORE1_DDR3
.neardata > CORE1_DDR3
.rodata > CORE1_DDR3

}

以上两种cmd文件生成的out文件连接仿真器是可以正常运行的

问题1:但由于在考虑spi boot ,主核的程序里在往boot magic addr上写入的地址是0x1x800000,而其他核的程序都放在DDR上所以感觉即使跳入了_c_int00()也不能正常找到对应的程序段(因为程序段在cmd里都放在DDR里了,不知道这样理解是否正确)?

基于上述问题考虑,所以将从核的text段和stack段定义在了L2里,cmd文件如下:

-x
-stack 0x10000
-heap 0x10000

MEMORY
{

VECTORS: origin = 0x00800000 length = 0x00000400
/*Local addresses*/
//LL2MEM: origin = 0x00800400 length = 0x0007FC00

/* M3 RAM */
MSMCRAM: origin = 0x0C000000 length = 0x00400000
DDR3RAM: origin=0x80000000 length=0x20000000 /*512*/

BOOT_CORE0: origin = 0x10800000 length = 0x000000c0
CORE0_L2: origin = 0x108000c0 length = 0x0007FF40
CORE0_DDR3: origin=0xa0000000 length=0x10000000

BOOT_CORE1: origin = 0x11800000 length = 0x000000c0
CORE1_L2: origin = 0x118000c0 length = 0x0007FF40
CORE1_DDR3: origin=0xb0000000 length=0x10000000

BOOT_CORE2: origin = 0x12800000 length = 0x000000c0
CORE2_L2: origin = 0x128000c0 length = 0x0007FF40
CORE2_DDR3: origin=0xc0000000 length=0x10000000

BOOT_CORE3: origin = 0x13800000 length = 0x000000c0
CORE3_L2: origin = 0x138000c0 length = 0x0007FF40
CORE3_DDR3: origin=0xd0000000 length=0x10000000

BOOT_CORE4: origin = 0x14800000 length = 0x000000c0
CORE4_L2: origin = 0x148000c0 length = 0x0007FF40
CORE4_DDR3: origin=0xe0000000 length=0x10000000
}
SECTIONS
{
.csl_vect: > VECTORS

/* Boot Memory Sections */
//.boot: > LL2MEM

/* Text Memory Sections */
.text: > CORE4_L2
.stack: > CORE4_L2

/* Data Memory Sections */
.data: > CORE4_DDR3
.cinit: > CORE4_DDR3
.bss: > CORE4_DDR3
.const: > CORE4_DDR3
.far: > CORE4_DDR3
.switch: > CORE4_DDR3
.sysmem: > CORE4_DDR3
.cio: > CORE4_DDR3

.heap > CORE4_DDR3
// .fardata > LL2MEM
// .neardata > LL2MEM
//.rodata > LL2MEM

//.INRAM > LL2MEM
//.MSRAM > MSMCRAM
//.EXRAM > DDR3RAM
.myboot
{
*.*<boot.obj>(.text)

} > BOOT_CORE4
}

在连接仿真器运行时出现问题:

核2和核4运行后无反应,点击暂停后出现does not contain frame information

C66xx_2: Trouble Reading Register ControlRegisters_CSR: (Error -1202 @ 0x41) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 5.1.232.0) 

等错误。

 问题2:spi boot的magic addr写入的是0x1x800000是不是意味着对应的程序段就要放在L2存储器的0x1x8000000开始的空间内,如果想把程序段都放在DDR里,需要如何修改cmd文件和magic地址内容?

问题3:RBL是如果搬移程序的,如果我的cmd文件里程序放在DDR里,首先RBL让核0跳转到0x10800000入口地址位置,然后它去哪里寻找对应的程序段呢?

问题4:主核里有pll ddr的初始化程序(platform_init()),从核的程序里还需要加入初始化的程序吗?

这里比较困惑也比较紧急,感谢回答

user6109135:

spi boot 启动方式,上电后,主核和从核的程序是如何搬运的,例如一开始在flash里面的程序会搬运到DDR还是L2?

user6109135:

为啥没人回复呀,急求回答

Shine:

请问在修改cmd文件之前,能多核加载吗?如果要把代码搬移到DDR,需要在生成烧写代码时配置SPI parameter table来配置DDR。

user6109135:

回复 Shine:

修改cmd文件之前,主核是定义在l2里的,从核程序放在DDR里的,主核单独可以加载,五个核一起就没法加载了。
所以如果不修改SPI parameter table,默认情况下,程序是自动被搬移到哪里呢?
为什么我把五个核的text段核stack段都定义在L2里,仿真都不能成功呀?

user6109135:

回复 Shine:

我现在遇到的问题好像是,只要把五个核的程序段都定义在各自的l2中,仿真器调试都不正常。

user6109135:

回复 Shine:

求回答

user6109135:

回复 Shine:

请问 配置SPI parameter table来配置DDR,这个具体怎么操作呢

Shine:

回复 user6109135:

先在仿真器模式下把程序调通,然后再去调试加载模式。先不要一下子使能5个核,调通core0+core1程序后,再慢慢将其他核打开,一步步来便于定位问题。

Shine:

回复 user6109135:

配置SPI parameter table来配置DDR,可以参考下面的boot例程。
processors.wiki.ti.com/…/KeystoneI_Bootloader_Resources_and_FAQ

另外,boot magic addr的地址是0x0087FFFC。bootloader的过程建议看一下bootloader文档。
www.ti.com/…/sprugy5

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