电流始终上不去,而且输出波形频率有时候正常,有时候是设定的一半,频率不稳定,而且最重要的是,占空比上不了50%,到50%以上就不稳定,芯片手册是这样说的,但是我们按要求做了,效果仍然不明显,不知道如何解决
8.3.2 Sub-Harmonic Oscillation
Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation) on top of the sensed inductor current shown in Figure 20. By choosing K≥1, the regulator will not be subject to sub-harmonic oscillation caused by a varying input voltage.
In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock cycle. If the magnitude of the end-of-cycle current error, dI1, caused by an initial perturbation, dI0, is less than the magnitude of dI0 or dI1/dI0 > -1, the perturbation naturally disappears after a few cycles. When dI1/dI0 < -1, the initial perturbation does not disappear, resulting in sub-harmonic oscillation in steady-state operation.
Johnsin Tao:
Hi带载能力下降首先要确认电感饱和电流足够,建议大于1.3倍以上的最大输出电流。其次重点确认layout, 功率回路尽量小,sense电阻layout上注意连接方式,以及尽量避免noise。
Johnsin Tao:
Hi带载能力下降首先要确认电感饱和电流足够,建议大于1.3倍以上的最大输出电流。其次重点确认layout, 功率回路尽量小,sense电阻layout上注意连接方式,以及尽量避免noise。