TI中文支持网我们在调试DSP6657与AFE 7225接口中遇到问题，希望寻求帮助，看是否能解决。
硬件上DSP6657利用UPP接口与AFE7225（CMOS）进行连接，时钟采用外部晶振32.768MHz，时钟采用差分输入，框图如下。
问题1：现在SPI控制读写AFE7225寄存器正常，UPP接口向AFE7225推送数据后，AFE7225输出DAC out没有任何输出，通过SPI接口读取AFE 7225 FIFO寄存器，数值一直为0，但FIFO read/write指针在按照时钟递增，不知道是怎么解决，请求帮助。
其中1.6657 UPP接口内部环路测试是正常的；2.利用AFE 7225测试模式发送数据，DSP6657可以通过UPP接收，并数据变化正常。
下图为UPP接口发送数据测试的时钟与数据线信号；这样信号是否正常，如果不正常UPP接口如何配置？配置的是DDR模式，配置代码如下。
图 1 AFE7225_DACCLK时钟与数据示波器图，黄色为时钟
下图为AFE 7225发送数据，UPP接口解析的时钟与数据信号。
图 2 AFE7225_ADCCLK时钟与数据示波器图，黄色为时钟
问题2：针对AFE 7225输入clkinp与CLkINN差分信号模式，对于这个输入信号幅度是否有要求，因为发现当输入幅值为1V峰峰值时， ADCDCLK输出是配置应该输出的2倍。
afe7225配置代码如下
spi_release();/* Claim the SPI controller */rtn = spi_claim(SPI_AFE7225, SPI_MAX_FREQ);if(rtn){PR_ERR(rtn);return -rtn;}gpioSetOutput(GPIO_19_AFE7225_CS);gpioClearOutput(GPIO_7_AFE7225_SYN);
//----------------
//Chip Control Set
//----------------rtn = afe_write(0x000, 0x02);//resetif (rtn){spi_release();return -1;}for(i = 0; i < 200; ++i){asm(" nop");}//Global power down & 3-statertn += afe_write(0x207, 0x00);//resetrtn += afe_write(0x208, 0x00);//resetrtn += afe_write(0x209, 0x00);//resetif (rtn){spi_release();return -1;}for(i = 0; i < 200; ++i){asm(" nop");}rtn = afe_write(0x20A, 0x02);//sdout & CMOS modeif (rtn){spi_release();return -1;}rtn = afe_read(0x20A, mid_buf);if (rtn || (mid_buf[0] != 0x02)){spi_release();return -1;}
//---------------------
// TX DAC Control
//---------------------rtn += afe_write(0x237, 0x00);//Full scalertn += afe_write(0x238, 0x00);//Full scalertn += afe_write(0x239, 0x00);//Full scaleif (rtn){spi_release();return -1;}
//---------------------
//Clocking Ctrl Setting
//---------------------//set clock as 32.758MHz / 4 = 8.192MHzrtn += afe_write(0x23C, 0x14);rtn += afe_write(0x23D, 0x00); //PLL Disablertn += afe_write(0xDB, 0x00); //DCC Disablertn += afe_write(0xF2, 0x00); //DCC Disableif (rtn){spi_release();return -1;}
//-------------------------
//Rx Digital Signal Chain
//-------------------------
#ifdef RX_SIGNAL_CHAIN_ON//enable decimation filter, then the output clock autimatically set to 4.096MHzrtn += afe_write(0x165, 0x03); //enable loopback mode & decimation filterrtn += afe_write(0x166, 0x00); //disable cmix, set as normal modertn += afe_write(0x167, 0x00); //power on all
#ifdef AFE_7225_SYN_ENrtn += afe_write(0x168, 0x00); //enable syncrtn += afe_write(0x169, 0x00); //src -sync pinrtn += afe_write(0x16A, 0x00); //sync bit -ignore
#elsertn += afe_write(0x168, 0x1F); //disable syncrtn += afe_write(0x169, 0x00); //src -sync pinrtn += afe_write(0x16A, 0x00); //sync bit -ignore
#endifrtn += afe_write(0x16B, 0x0); //rx QMC off//0x16C~0x173 not work when QMC module is powered down;
//set nco module//set nco freqeucy word 2^27 Fs/32 = 8.192MHz / 32 = 256KHz//rtn += afe_write(0x174, 0x08);rtn += afe_write(0x174, 0x00);rtn += afe_write(0x175, 0x00);rtn += afe_write(0x176, 0x00);rtn += afe_write(0x177, 0x00);rtn += afe_write(0x178, 0x00);rtn += afe_write(0x179, 0x00);rtn += afe_write(0x17A, 0x88); //disable mix gain -2.5dB & set coarse samples 256rtn += afe_write(0x17B, 0x88); //disable PWR * NCO sync pin , no need sync//clear power meter INTGR_CNT, SYNC_CNT, INRRV_CNTrtn += afe_write(0x17C, 0x00);rtn += afe_write(0x17D, 0x00);rtn += afe_write(0x17E, 0x00);rtn += afe_write(0x17F, 0x00);rtn += afe_write(0x180, 0x00);rtn += afe_write(0x181, 0x00);rtn += afe_write(0x182, 0x00); //disable power meter, set as fine mode, set output as I2+Q2rtn += afe_write(0x42, 0x8);rtn += afe_write(0x31, 0x4);rtn += afe_write(0x37, 0x4);if (rtn){spi_release();return -1;}//0x183~189 represent PWR_OP_I, read only//0x18A~191 represent PWR_OP_Q, read only//0x1B2 for coarse power meter
#endif
//-------------------------
//Tx Digital Signal Chain
//-------------------------
#ifdef TX_SIGNAL_CHAIN_ONrtn += afe_write(0x103, 0x00);// power on channel A & channel Brtn += afe_write(0x104, 0xF0);//fifo modertn += afe_write(0x105, 0x08);//rx to tx loopback disable, store fifo PTRSrtn += afe_write(0x106, 0x05);//tx 2 interpolation & lowpassrtn += afe_write(0x107, 0x01);//Enable cmix set Normalrtn += afe_write(0x108, 0x00);//output order
#ifdef AFE_7225_SYN_ENrtn += afe_write(0x10B, 0x3A);//all syc disablertn += afe_write(0x10C, 0x00);//syn srcrtn += afe_write(0x10D, 0x00);//syn serial bit
#elsertn += afe_write(0x10B, 0x3A);//all syc disablertn += afe_write(0x10C, 0x00);//syn srcrtn += afe_write(0x10D, 0x00);//syn serial bit
#endif//disbalertn += afe_write(0x10E, 0x00);// diable QMCrtn += afe_write(0x10F, 0x00);//QMCrtn += afe_write(0x110, 0x00);//QMCrtn += afe_write(0x111, 0x00);//QMCrtn += afe_write(0x112, 0x00);//QMCrtn += afe_write(0x113, 0x00);//QMCrtn += afe_write(0x114, 0x00);//QMCrtn += afe_write(0x115, 0x00);//QMCrtn += afe_write(0x116, 0x00);//QMC//set nco freqeucy word 2^27 Fs/32 = 8.192MHz / 32 = 256KHzrtn += afe_write(0x117, 0x00);//rtn += afe_write(0x117, 0x08);rtn += afe_write(0x118, 0x00);rtn += afe_write(0x119, 0x00);rtn += afe_write(0x11A, 0x00);rtn += afe_write(0x11B, 0x00);rtn += afe_write(0x11C, 0x00);rtn += afe_write(0x11D, 0x08); //enable fine mix, defaultrtn += afe_write(0x11E, 0x80); //rtn += afe_write(0x13F, 0xC0); ////0x120~0x13F is used in fifo modeif (rtn){spi_release();return -1;}rtn = afe_write(0x24D, 0x00);if (rtn){spi_release();return -1;}
#endifrtn = afe_read(0x141, mid_buf);if (rtn){spi_release();return -1;}gpioClearOutput(GPIO_7_AFE7225_SYN);gpioSetOutput(GPIO_7_AFE7225_SYN);for(i = 0; i < 200; ++i){asm(" nop");}gpioClearOutput(GPIO_7_AFE7225_SYN);rtn = afe_read(0x141, mid_buf);if (rtn){spi_release();return -1;}
Upp接口的配置如下
// Disable L1D cache*(volatile uint32_t *)(0x01840040) &= 0xFFFFFFF0;//step1:pinmux & clock UPP_2XTXCLK_pin*(volatile uint32_t *) (0x02620584) = 0x00000001;*(volatile uint32_t *) (0x0262016C) = 0x00000001;//clock*(volatile uint32_t *) (0x02620588) = 0x06070607;//upp priorty
#define UPP_DDR_MODE
//#define UPP_LOOPBACK//check PIDpid = UPP_REG->UPPID;if(pid != 0x44231100u){DEBUG_PRINT(printk("PID error!"));return -1;}//step2: power clock, default open//step3: resetCSL_FINS (UPP_REG->UPPCR, UPP_UPPCR_EN, CSL_UPP_UPPCR_EN_DISABLE);while (CSL_FEXT(UPP_REG->UPPCR, UPP_UPPCR_DB) == CSL_UPP_UPPCR_DB_ACTIVE)asm(" nop");CSL_FINS (UPP_REG->UPPCR, UPP_UPPCR_SWRST, CSL_UPP_UPPCR_SWRST_RESET);CSL_FINS (UPP_REG->UPPCR, UPP_UPPCR_FREE, CSL_UPP_UPPCR_FREE_DISABLE);//step4: runingplatform_delaycycles(200);CSL_FINS (UPP_REG->UPPCR, UPP_UPPCR_SWRST, CSL_UPP_UPPCR_SWRST_RUNNING);//step5: Program uPP configuration register//UPCTLCSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DPFB, CSL_UPP_UPCTL_DPFB_RJZE);CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DPWB, CSL_UPP_UPCTL_DPWB_12BIT);CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_IWB, CSL_UPP_UPCTL_IWB_16BIT);
#ifdef UPP_SDR_MODECSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DRB, CSL_UPP_UPCTL_DRB_SINGLE);
#elif defined(UPP_DDR_MODE)CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DRB, CSL_UPP_UPCTL_DRB_DOUBLE);
#endifCSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DPFA, CSL_UPP_UPCTL_DPFA_RJZE);CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DPWA, CSL_UPP_UPCTL_DPWA_12BIT);CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_IWA, CSL_UPP_UPCTL_IWA_16BIT);
#ifdef UPP_SDR_MODECSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DRA, CSL_UPP_UPCTL_DRA_SINGLE);
#elif defined(UPP_DDR_MODE)CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DRA, CSL_UPP_UPCTL_DRA_DOUBLE);
#endifCSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_DDRDEMUX, CSL_UPP_UPCTL_DDRDEMUX_DISABLE);CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_SDRTXIL, CSL_UPP_UPCTL_SDRTXIL_DISABLE);CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_CHN, CSL_UPP_UPCTL_CHN_TWO);CSL_FINS (UPP_REG->UPCTL, UPP_UPCTL_MODE, CSL_UPP_UPCTL_MODE_DUPLEX0);//UPICRCSL_FINS (UPP_REG->UPICR, UPP_UPICR_TRISB, CSL_UPP_UPICR_TRISB_DISABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_CLKINVB, CSL_UPP_UPICR_CLKINVB_NORMAL);
#ifdef PLATFORM_6657// 1000 / 6 * (3 + 1) = 4.096 MHz// 1000 / 6 * (7 + 1) = 2.048 MHz// 1000 / 6 * (15 + 1) = 10.416 MHzCSL_FINS (UPP_REG->UPICR, UPP_UPICR_CLKDIVB, 15);//clock
#elif defined(CHANNEL_SIM_6657)// 32.768 / 2 * (3 + 1) = 4.096 MHz// 32.768 / 2 * (7 + 1) = 2.048 MHz// 32.768 / 2 * (15 + 1) = 1.024 MHzCSL_FINS (UPP_REG->UPICR, UPP_UPICR_CLKDIVB, 3);//clock
#endifCSL_FINS (UPP_REG->UPICR, UPP_UPICR_WAITB, CSL_UPP_UPICR_WAITB_ENABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_ENAB, CSL_UPP_UPICR_ENAB_ENABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_STARTB, CSL_UPP_UPICR_STARTB_ENABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_WAITPOLB, CSL_UPP_UPICR_WAITPOLB_NORMAL);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_ENAPOLB, CSL_UPP_UPICR_ENAPOLB_NORMAL);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_STARTPOLB, CSL_UPP_UPICR_STARTPOLB_NORMAL);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_TRISA, CSL_UPP_UPICR_TRISA_DISABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_CLKINVA, CSL_UPP_UPICR_CLKINVA_NORMAL);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_CLKDIVA, 3);//clockCSL_FINS (UPP_REG->UPICR, UPP_UPICR_WAITA, CSL_UPP_UPICR_WAITA_DISABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_ENAA, CSL_UPP_UPICR_ENAA_DISABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_STARTA, CSL_UPP_UPICR_STARTA_DISABLE);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_WAITPOLA, CSL_UPP_UPICR_WAITPOLA_NORMAL);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_ENAPOLA, CSL_UPP_UPICR_ENAPOLA_NORMAL);CSL_FINS (UPP_REG->UPICR, UPP_UPICR_STARTPOLA, CSL_UPP_UPICR_STARTPOLA_NORMAL);//UPIVRCSL_FINS (UPP_REG->UPIVR, UPP_UPIVR_VALB, 0xAA55);CSL_FINS (UPP_REG->UPIVR, UPP_UPIVR_VALA, 0x55AA);//UP TCRCSL_FINS (UPP_REG->UPTCR, UPP_UPTCR_TXSIZEB, CSL_UPP_UPTCR_TXSIZEB_256B);CSL_FINS (UPP_REG->UPTCR, UPP_UPTCR_TXSIZEA, CSL_UPP_UPTCR_TXSIZEA_256B);CSL_FINS (UPP_REG->UPTCR, UPP_UPTCR_RDSIZEQ, CSL_UPP_UPTCR_RDSIZEQ_256B);CSL_FINS (UPP_REG->UPTCR, UPP_UPTCR_RDSIZEI, CSL_UPP_UPTCR_RDSIZEI_256B);//UPDLB
#ifdef UPP_LOOPBACKCSL_FINS (UPP_REG->UPDLB, UPP_UPDLB_BA, CSL_UPP_UPDLB_BA_ENABLE);
#elseCSL_FINS (UPP_REG->UPDLB, UPP_UPDLB_BA, CSL_UPP_UPDLB_BA_DISABLE);
#endifCSL_FINS (UPP_REG->UPDLB, UPP_UPDLB_AB, CSL_UPP_UPDLB_AB_DISABLE);//step6: interruptCSL_FINS (UPP_REG->UPIES, UPP_UPIES_EOLQ, CSL_UPP_UPIES_EOLQ_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_EOWQ, CSL_UPP_UPIES_EOWQ_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_ERRQ, CSL_UPP_UPIES_ERRQ_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_UORQ, CSL_UPP_UPIES_UORQ_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_DPEQ, CSL_UPP_UPIES_DPEQ_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_EOLI, CSL_UPP_UPIES_EOLI_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_EOWI, CSL_UPP_UPIES_EOWI_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_ERRI, CSL_UPP_UPIES_ERRI_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_UORI, CSL_UPP_UPIES_UORI_SET);CSL_FINS (UPP_REG->UPIES, UPP_UPIES_DPEI, CSL_UPP_UPIES_DPEI_SET);
Shine：
因为upp这边自环模式没什么问题，可以排除upp的基本的配置问题。建议去数据转换器论坛咨询一下AFE7225，看需要怎么配置寄存器。
e2echina.ti.com/…/
underwood you：
回复 Shine:
是否能够帮忙将帖子转入 数据转换器论坛，还是说要重新发布
Shine：
回复 underwood you:
转过去了。
